Kyung Whan Kim
According to our database1,
Kyung Whan Kim
authored at least 9 papers
between 2010 and 2019.
Collaborative distances:
Collaborative distances:
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Bibliography
2019
A 1.1V 1ynm 6.4Gb/s/pin 16Gb DDR5 SDRAM with a Phase-Rotator-Based DLL, High-Speed SerDes and RX/TX Equalization Scheme.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2016
18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the International SoC Design Conference, 2016
2015
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM.
Proceedings of the Symposium on VLSI Circuits, 2014
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.
IEEE J. Solid State Circuits, 2012
2010
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010