Kyung-Soo Ha
Orcid: 0000-0002-2680-3675
According to our database1,
Kyung-Soo Ha
authored at least 14 papers
between 2006 and 2020.
Collaborative distances:
Collaborative distances:
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Bibliography
2020
IEEE J. Solid State Circuits, 2020
2019
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM.
IEEE J. Solid State Circuits, 2018
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2016
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation.
IEEE J. Solid State Circuits, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2009
A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN.
IEEE J. Solid State Circuits, 2009
A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006