Kyung Rok Kim

According to our database, Kyung Rok Kim authored at least 8 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Energy Efficient Ternary Device in 28-nm CMOS Technology with Excellent Short-Channel Effect Immunity and Variation Tolerance Characteristics.

Woo-Seok Kim, Young-Eun Choi, Myoung Kim, Min Woo Ryu, Kyung Rok Kim

Proceedings of the Device Research Conference, 2023

Low Power and High Density Ternary-SRAM for Always-on Applications.

Young-Eun Choi, Woo-Seok Kim, Myoung Kim, Min-Woo Ryu, Kyung Rok Kim

Proceedings of the Device Research Conference, 2023

2020

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits.

Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2017

CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits.

Sunhae Shin, Esan Jang, Jae Won Jeong, Kyung Rok Kim

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

A Novel Ternary Multiplier Based on Ternary CMOS Compact Model.

Yesung Kang, Jaewoo Kim, Sunmin Kim, Sunhae Shin, E-San Jang, Jae Won Jeong, Kyung Rok Kim, Seokhyeong Kang

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

2013

Plasmonic Terahertz Wave Detectors Based on Silicon Field-Effect Transistors.

Min-Woo Ryu, Sung-Ho Kim, Hee Cheol Hwang, Kibog Park, Kyung Rok Kim

IEICE Trans. Electron., 2013

2010

Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs.

Seongjae Cho, In Man Kang, Kyung Rok Kim

IEICE Electron. Express, 2010

2003

Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic.

Ki-Whan Song, Sang-Hoon Lee, Dae Hwan Kim, Kyung Rok Kim, Jaewoo Kyung, Gwanghyeon Baek, Chun-An Lee, Jong Duk Lee, Byung-Gook Park

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003