Kyung-Ju Cho

According to our database¹, Kyung-Ju Cho authored at least 20 papers between 2004 and 2017.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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PhD thesis

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On csauthors.net:

Bibliography

2017

Low-latency and memory-efficient SDF IFFT processor design for 3GPP LTE.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

2016

Low latency IFFT design for 3GPP LTE.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

2014

Memory efficient DIT-based SDF IFFT for OFDM systems.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

2013

Memory efficient IFFT design for OFDM-based applications.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2013

2012

Memory Size Reduction Technique of SDF IFFT Architecture for OFDM-Based Applications.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2012

Efficient unsigned squarer design techniques.

[BibT_eX]

[DOI]

Kyung-Ju Cho

IEICE Electron. Express, 2012

Efficient IFFT architecture design for OFDM applications.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

2011

A memory size reduction method of pipelined IFFT processor for OFDM systems.

[BibT_eX]

[DOI]

In-Gul Jang

Kyung-Ju Cho

IEICE Electron. Express, 2011

Fixed-Width Modified Booth Multiplier Design Based on Error Bound Analysis.

[BibT_eX]

[DOI]

Proceedings of the Multimedia, Computer Graphics and Broadcasting, 2011

2010

Implementation of FlexRay CC and BG protocols with application to a robot system.

[BibT_eX]

[DOI]

Int. J. Comput. Aided Eng. Technol., 2010

Fixed-Width Group CSD Multiplier Design.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

CSD-Based Programmable Multiplier Design for Predetermined Coefficient Groups.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2008

Implementation of FlexRay CC and BG Protocols with Application to a Robot System.

[BibT_eX]

Proceedings of the 2008 International Conference on Modeling, 2008

Implementation of FlexRay communication controller protocol with application to a robot system.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Constant multiplier design using specialized bit pattern adders.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007

Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Low Power Small Area Modified Booth Multiplier Design for Predetermined Coefficients.

[BibT_eX]

[DOI]

Yong-Eun Kim

Kyung-Ju Cho

Jin-Gyun Chung

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Adaptive Error Compensation for Low Error Fixed-Width Squarers.

[BibT_eX]

[DOI]

Kyung-Ju Cho

Jin-Gyun Chung

IEICE Trans. Inf. Syst., 2007

Hardware Efficient QR Decomposition for GDFE.

[BibT_eX]

[DOI]

Kyung-Ju Cho

Yi-Nan Xu

Jin-Gyun Chung

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

2004

Design of low-error fixed-width modified booth multiplier.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Kyung-Ju Cho

Timeline

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