Kyung-Hoae Koo
According to our database1,
Kyung-Hoae Koo
authored at least 6 papers
between 2007 and 2017.
Collaborative distances:
Collaborative distances:
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Bibliography
2017
5.6 Mb/mm<sup>2</sup> 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology.
IEEE J. Solid State Circuits, 2017
2016
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 0.094um<sup>2</sup> high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist.
Proceedings of the Symposium on VLSI Circuits, 2015
2010
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs.
Proceedings of the NOCS 2010, 2010
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007