Kyumyung Choi

Orcid: 0000-0001-8153-8344

According to our database1, Kyumyung Choi authored at least 7 papers between 1995 and 2024.

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Bibliography

2024
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024

Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model.
Proceedings of the 2024 International Symposium on Physical Design, 2024

2022
Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2008
A fast two-pass HDL simulation with on-demand dump.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

1999
A flexible datapath allocation method for architectural synthesis.
ACM Trans. Design Autom. Electr. Syst., 1999

1995
Exploration of Area and Performance Optimized Datapath Design Using Realistic Cost Metrics.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995


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