Kyuho Jason Lee
Orcid: 0000-0002-4047-1013Affiliations:
- Ulsan National Institute of Science and Technologym, Korea
- Korea Advanced Institute of Science and Technology (KAIST), Korea (former)
According to our database1,
Kyuho Jason Lee
authored at least 45 papers
between 2013 and 2025.
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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Bibliography
2025
A 701.7 TOPS/W Compute-in-Memory Processor With Time-Domain Computing for Spiking Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2025
IEEE J. Solid State Circuits, January, 2025
2024
IEEE Trans. Circuits Syst. I Regul. Pap., August, 2024
An Energy-Efficient, Unified CNN Accelerator for Real-Time Multi-Object Semantic Segmentation for Autonomous Vehicle.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024
20.6 LSPU: A Fully Integrated Real-Time LiDAR-SLAM SoC with Point-Neural-Network Segmentation and Multi-Level kNN Acceleration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
An Energy-Efficient 3D Point Neural Network Accelerator with Fine-grained LiDAR-SoC Pipeline Structure.
Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design, 2024
A 422.1 Mpixels/J Tile-based 4K Super Resolution Processor with Variable Bit Compression.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
LSPU: A 20.7 ms Low-Latency Point Neural Network-Based 3D Perception and Semantic LiDAR SLAM System-on-Chip for Autonomous Driving System.
Proceedings of the 36th IEEE Hot Chips Symposium, 2024
A Low-power and Real-time Semantic LiDAR SLAM Processor with Point Neural Network Segmentation and kNN Acceleration for Mobile Robots.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024
A Low-power 3D Point Clouds Matching Processor with 1D-CNN Prediction and CAM-based In-memory kNN Searching.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024
2023
A Ternary Neural Network Computing-in-Memory Processor With 16T1C Bitcell Architecture.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2023
A 701.7 TOPS/W Time-Domain Spiking Neural Network Compute-in-Memory Processor with 9T1C Bitcell.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
2022
An Energy-Efficient CNN Accelerator for Multi-object Real-Time Semantic Segmentation in Autonomous Vehicle.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Adv. Comput., 2021
Proceedings of the 18th International SoC Design Conference, 2021
2020
IEEE Trans. Circuits Syst., 2020
17.3 A -58dBc-Worst-Fractional-Spur and -234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020
2018
A 9.02mW CNN-stereo-based real-time 3D hand-gesture recognition processor for smart mobile devices.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A 502-GOPS and 0.984-mW Dual-Mode Intelligent ADAS SoC With Real-Time Semiglobal Matching and Intention Prediction for Smart Automotive Black Box System.
IEEE J. Solid State Circuits, 2017
A 1.4-m $\Omega$ -Sensitivity 94-dB Dynamic-Range Electrical Impedance Tomography SoC and 48-Channel Hub-SoC for 3-D Lung Ventilation Monitoring System.
IEEE J. Solid State Circuits, 2017
IEEE J. Solid State Circuits, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
A Real-Time and Energy-Efficient Embedded System for Intelligent ADAS with RNN-Based Deep Risk Prediction using Stereo Camera.
Proceedings of the Computer Vision Systems - 11th International Conference, 2017
An ultra-low-power and mixed-mode event-driven face detection SoC for always-on mobile applications.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2016
A CMOS Image Sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 2.71 nJ/Pixel Gaze-Activated Object Recognition System for Low-Power Mobile Smart Glasses.
IEEE J. Solid State Circuits, 2016
A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 42.5µW 100 kb/s Super-Regenerative Transceiver for Body Channel Communication.
IEEE J. Solid State Circuits, 2016
14.2 A 502GOPS and 0.984mW dual-mode ADAS SoC with RNN-FIS engine for intention prediction in automotive black-box system.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
An intelligent ADAS processor with real-time semi-global matching and intention prediction for 720p stereo vision.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
An energy-efficient parallel multi-core ADAS processor with robust visual attention and workload-prediction DVFS for real-time HD stereo stream.
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
2015
A Vocabulary Forest Object Matching Processor With 2.07 M-Vector/s Throughput and 13.3 nJ/Vector Per-Vector Energy for Full-HD 60 fps Video Object Recognition.
IEEE J. Solid State Circuits, 2015
A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications.
IEEE J. Solid State Circuits, 2015
18.1 A 2.71nJ/pixel 3D-stacked gaze-activated object-recognition system for low-power mobile HMD applications.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Intelligent task scheduler with high throughput NoC for real-time mobile object recognition SoC.
Proceedings of the ESSCIRC Conference 2015, 2015
A keypoint-level parallel pipelined object recognition processor with gaze activation image sensor for mobile smart glasses system.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
2014
IEEE Micro, 2014
A Vocabulary Forest-based object matching processor with 2.07M-vec/s throughput and 13.3nJ/vector energy in full-HD resolution.
Proceedings of the Symposium on VLSI Circuits, 2014
10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
2013
A 646GOPS/W multi-classifier many-core processor with cortex-like architecture for super-resolution recognition.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A multi-modal and tunable Radial-Basis-Funtion circuit with supply and temperature compensation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling.
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013