Kyu-Myung Choi
According to our database1,
Kyu-Myung Choi
authored at least 26 papers
between 2003 and 2024.
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Bibliography
2024
BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2020
SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage.
Integr., 2020
Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2019
SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
2018
Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2015
A 14 nm FinFET 128 Mb SRAM With V<sub>MIN</sub> Enhancement Techniques for Low-Power Applications.
IEEE J. Solid State Circuits, 2015
2014
13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs.
ACM Trans. Design Autom. Electr. Syst., 2010
An industrial perspective of 3D IC integration technology: from the viewpoint of design technology.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
45nm Low-power Embedded Pseudo-SRAM with ECC-based Auto-adjusted Self-refresh Scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
An Open-Loop Flow Control Scheme Based on the Accurate Global Information of On-Chip Communication.
Proceedings of the Design, Automation and Test in Europe, 2008
Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution.
Proceedings of the Design, Automation and Test in Europe, 2008
A practical approach of memory access parallelization to exploit multiple off-chip DDR memories.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Creation and utilization of a virtual platform for embedded software optimization: : an industrial case study.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture.
Proceedings of the 2005 Design, 2005
2004
Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design.
Proceedings of the 2004 Design, 2004
2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003