Kyoya Takano

Orcid: 0000-0001-7711-3191

According to our database1, Kyoya Takano authored at least 39 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
25.9-Gb/s 259-GHz Phased-Array CMOS Receiver Module with 28° Steering Range.
Proceedings of the IEEE Radio and Wireless Symposium, 2024

2023
A Compact Fully-Differential Distributed Amplifier with Coupled Inductors in 0.18-µm CMOS Technology.
IEICE Trans. Electron., November, 2023

A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC.
IEICE Trans. Electron., October, 2023

A 0.0058-mm<sup>2</sup> Inductor-Less CMOS Active Balun With Gain and Phase Errors Within -0.1 ± 0.2 dB and -0.18 ± 1.17<sup>°</sup> From DC to 8 GHz.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

39 - 67 GHz CMOS Multistage Power Amplifier With Two-Way Power Stage.
Proceedings of the International Conference on IC Design and Technology, 2023

A 2D Beam-Steerable 252-285-GHz 25.8-Gbit/s CMOS Receiver Module.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2022
A 76-Gbit/s 265-GHz CMOS Receiver With WR-3.4 Waveguide Interface.
IEEE J. Solid State Circuits, 2022

A 50 Gbps 49 mW CMOS Analog Multiplexer for a DAC Bandwidth Tripler.
Proceedings of the 2022 IEEE Radio and Wireless Symposium, 2022

2021
300-GHz-Band OFDM Video Transmission with CMOS TX/RX Modules and 40dBi Cassegrain Antenna toward 6G.
IEICE Trans. Electron., 2021

A Broadband Active Balun with Inductor-Less Active Peaking and Imbalance Correction.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Design of an Area-Efficient Differential Distributed Amplifier Based on the Theory of Differential Transmission Lines.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

DAC Bandwidth Tripler with 3: 1 Image-Rejection Analog Multiplexer.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

Frequency-Interleaved ADC with RF Equivalent Ideal Filter for Broadband Optical Communication Receivers.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

A 272-GHz CMOS Analog BPSK/QPSK Demodulator for IEEE 802.15.3d.
Proceedings of the 47th ESSCIRC 2021, 2021


2018
32-Gbit/s CMOS Receivers in 300-GHz Band.
IEICE Trans. Electron., 2018

300-GHz CMOS transmitter module with built-in waveguide transition on a multilayered glass epoxy PCB.
Proceedings of the 2018 IEEE Radio and Wireless Symposium, 2018

Power-amplifier-inserted Transversal Filter that Recovers Quantization Noise Power by CMOS Rectifier.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A 37-GHz-Input Divide-by-36 Injection-Locked Frequency Divider with 1.6-GHz Lock Range.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
17.9 A 105Gb/s 300GHz CMOS transmitter.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A 300 GHz CMOS Transmitter With 32-QAM 17.5 Gb/s/ch Capability Over Six Channels.
IEEE J. Solid State Circuits, 2016

Compact 141-GHz Differential Amplifier with 20-dB Peak Gain and 22-GHz 3-dB Bandwidth.
IEICE Trans. Electron., 2016

20.1 A 300GHz 40nm CMOS transmitter with 32-QAM 17.5Gb/s/ch capability over 6 channels.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Tehrahertz CMOS Design for Low-Power and High-Speed Wireless Communication.
IEICE Trans. Electron., 2015

124-GHz CMOS quadrature voltage-controlled oscillator with fundamental injection locking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
135GHz 98mW 10Gbps CMOS Amplitude Shift Keying Transmitter and Receiver Chipset.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

E-Band 65nm CMOS Low-Noise Amplifier Design Using Gain-Boost Technique.
IEICE Trans. Electron., 2014

2013
98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits.
IEEE J. Solid State Circuits, 2013

Modeling of Short-Millimeter-Wave CMOS Transmission Line with Lossy Dielectrics with Specific Absorption Spectrum.
IEICE Trans. Electron., 2013

A 120 GHz/140 GHz Dual-Channel OOK Receiver Using 65 nm CMOS Technology.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers.
Proceedings of the 2013 IEEE Radio and Wireless Symposium, 2013

2012
Bias-Voltage-Dependent Subcircuit Model for Millimeter-Wave CMOS Circuit.
IEICE Trans. Electron., 2012

A 120-GHz Transmitter and Receiver Chipset with 9-Gbps Data Rate Using 65-nm CMOS Technology.
IEICE Trans. Electron., 2012

135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Analysis of De-Embedding Error Cancellation in Cascade Circuit Design.
IEICE Trans. Electron., 2011

Device Modeling Techniques for High-Frequency Circuits Design Using Bond-Based Design at over 100 GHz.
IEICE Trans. Electron., 2011

140GHz CMOS amplifier with group delay variation of 10.2ps and 0.1dB bandwidth of 12GHz.
IEICE Electron. Express, 2011

2008
4.8 GHz CMOS Frequency Multiplier Using Subharmonic Pulse-Injection Locking for Spurious Suppression.
IEICE Trans. Electron., 2008

2007
A Scalable Model of Shielded Capacitors Using Mirror Image Effects.
IEICE Trans. Electron., 2007


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