Kyongsu Lee

Orcid: 0000-0002-0534-6452

According to our database1, Kyongsu Lee authored at least 17 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021
Design and Analysis of a Low-Power Ternary SRAM.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A Smart Contact Lens Controller IC Supporting Dual-Mode Telemetry With Wireless-Powered Backscattering LSK and EM-Radiated RF Transmission Using a Single-Loop Antenna.
IEEE J. Solid State Circuits, 2020

High-speed transceiver network for in-vehicle communication system.
Proceedings of the International SoC Design Conference, 2020

2019
A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System.
IEICE Trans. Electron., 2019

A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2016
A 0.8-to-6.5 Gb/s Continuous-Rate Reference-Less Digital CDR With Half-Rate Common-Mode Clock-Embedded Signaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 200-Mb/s to 3-Gb/s wide-band referenceless CDR using bidirectional frequency detector.
Proceedings of the International SoC Design Conference, 2016

2015
Precise time-difference repetition for TDC with delay mismatch cancelling scheme.
IEICE Electron. Express, 2015

On-chip jitter tolerance measurement technique for CDR circuits.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Half-Rate Clock-Embedded Source Synchronous Transceivers in 130-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A 1.1 mW/Gb/s 10 Gbps half-rate clock-embedded transceiver for high-speed links in 65 nm CMOS.
IEICE Electron. Express, 2014

Avoiding noise frequency interference with binary phase pulse driving and CDS for capacitive TSP controller.
IEICE Electron. Express, 2014


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