Kyoji Yamashita

According to our database, Kyoji Yamashita authored at least 7 papers between 2001 and 2005.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2005

A Compact Model of the Pinch-off Region of 100 nm MOSFETs Based on the Surface-Potential.

Dondee Navarro, Takeshi Mizoguchi, Masami Suetake, Kazuya Hisamitsu, Hiroaki Ueno, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

IEICE Trans. Electron., 2005

1/<i>f</i>-Noise Characteristics in 100 nm-MOSFETs and Its Modeling for Circuit Simulation.

Shizunori Matsumoto, Hiroaki Ueno, Satoshi Hosokawa, Toshihiko Kitamura, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Tatsuya Ohguro, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

IEICE Trans. Electron., 2005

A Test Structure for Two-Dimensional Analysis of MOSFETs by Hot-Carrier-Induced Photoemission.

Toshihiro Matsuda, Hiroaki Takeuchi, Akira Muramatsu, Hideyuki Iwata, Takashi Ohzone, Kyoji Yamashita, Norio Koike, Ken-ichiro Tatsuuma

IEICE Trans. Electron., 2005

2003

Temperature-independence-point properties for 0.1μm-scale pocket-implant technologies and the impact on circuit design.

Kazuya Hisamitsu, Hiroaki Ueno, Masayasu Tanaka, Daisuke Kitamaru, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Circuit Simulation Models for Coming MOSFET Generations.

Mitiko Miura-Mattausch, Hiroaki Ueno, Hans Jürgen Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2001

Test-circuit-based extraction of inter- and intra-chip MOSFET-performance variations for analog-design reliability.

Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Y. Tatsumi, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Terufumi Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

Correlation method of circuit-performance and technology fluctuations for improved design reliability.

D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Mitiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama

Proceedings of ASP-DAC 2001, 2001