Kyoichi Nagata
According to our database1,
Kyoichi Nagata
authored at least 3 papers
between 1988 and 2000.
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Bibliography
2000
A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme.
IEEE J. Solid State Circuits, 2000
1996
IEEE J. Solid State Circuits, 1996
1988
Proceedings of the IEEE International Workshop on Intelligent Robots and Systems '88, Proceedings. IROS 1988, Tokyo, Japan, October 31, 1988