Kyohei Yamaguchi
According to our database1,
Kyohei Yamaguchi
authored at least 6 papers
between 2007 and 2014.
Collaborative distances:
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Bibliography
2014
MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism.
IEICE Trans. Inf. Syst., 2014
2013
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013
2012
Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification.
IEICE Trans. Inf. Syst., 2012
Proceedings of the 21st IEEE International Symposium on Robot and Human Interactive Communication, 2012
2011
Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
2007
Proceedings of the 2007 IEEE/RSJ International Conference on Intelligent Robots and Systems, October 29, 2007