Kyle Kuan

According to our database, Kyle Kuan authored at least 9 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation.

Kyle Kuan, Tosiron Adegbija

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2021

Advancing STTRAM Caches for Runtime Adaptable Energy-Efficient Microarchitectures.

Kyle Kuan

PhD thesis, 2021

2020

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design.

Kyle Kuan, Tosiron Adegbija

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches.

Kyle Kuan, Tosiron Adegbija

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems.

Kyle Kuan, Tosiron Adegbija

IEEE Trans. Computers, 2019

Energy and Performance Analysis of STTRAM Caches for Mobile Applications.

Kyle Kuan, Tosiron Adegbija

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning.

Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija

Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache.

Kyle Kuan, Tosiron Adegbija

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

LARS: Logically adaptable retention time STT-RAM cache for embedded systems.

Kyle Kuan, Tosiron Adegbija

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018