Kwanyeob Chae
Orcid: 0000-0002-1771-593X
According to our database1,
Kwanyeob Chae
authored at least 17 papers
between 2004 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection.
IEEE J. Solid State Circuits, January, 2024
2023
A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2020
22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
Proceedings of the International SoC Design Conference, 2018
2017
23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2014
Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A Dynamic Timing Error Prevention Technique in Pipelines With Time Borrowing and Clock Stretching.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2013
On the impact of 3D integration on high-throughput sensor information processing: A case study with image sensing.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2012
All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in a Low-Voltage Operation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Low-power design under variation using error prevention and error tolerance (invited paper).
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2004
High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study.
Proceedings of the 2004 Design, 2004