Kwanho Kim
Orcid: 0000-0002-9487-2365
According to our database1,
Kwanho Kim
authored at least 63 papers
between 2000 and 2025.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
A self-imitation learning approach for scheduling evaporation and encapsulation stages of OLED display manufacturing systems.
Robotics Comput. Integr. Manuf., 2025
2024
Accuracy of a Large Language Model in Distinguishing Anti- And Pro-vaccination Messages on Social Media: The Case of Human Papillomavirus Vaccination.
CoRR, 2024
An incremental learning approach to dynamic parallel machine scheduling with sequence-dependent setups and machine eligibility restrictions.
Appl. Soft Comput., 2024
Proceedings of the 33rd IEEE International Symposium on Industrial Electronics, 2024
2023
Self-growth learning-based machine scheduler to minimize setup time and tardiness in OLED display semiconductor manufacturing.
Appl. Soft Comput., September, 2023
Machine Learning-Based Day-Ahead Prediction of Price-Setting Scheduled Energy in the Korean Electricity Trading Mechanism.
IEEE Access, 2023
Proceedings of the 62nd Annual Conference of the Society of Instrument and Control Engineers, 2023
Dynamic Obstacle Avoidance in a Complex Environment using Meta-heuristic Algorithms for 4-wheel Robot.
Proceedings of the International Workshop on Intelligent Systems, 2023
Proceedings of the International Workshop on Intelligent Systems, 2023
2022
Business transaction recommendation for discovering potential business partners using deep learning.
Expert Syst. Appl., 2022
A 1-Tb, 4b/Cell, 176-Stacked-WL 3D-NAND Flash Memory with Improved Read Latency and a 14.8Gb/mm2 Density.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
The Information Ecosystem of Online Groups with Anti- and Pro-vaccine Views on Facebook.
CoRR, 2021
2020
Comparison Analysis of Machine Learning Techniques for Photovoltaic Prediction Using Weather Sensor Data.
Sensors, 2020
13.2 A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A case-based reasoning approach to fast optimization of travel routes for large-scale AS/RSs.
J. Intell. Manuf., 2019
2017
Sensors, 2017
A Biological Signal-Based Stress Monitoring Framework for Children Using Wearable Devices.
Sensors, 2017
2016
Sensors, 2016
i-RM: An intelligent risk management framework for context-aware ubiquitous cold chain logistics.
Expert Syst. Appl., 2016
2014
IEICE Trans. Inf. Syst., 2014
An analysis on movement patterns between zones using smart card data in subway networks.
Int. J. Geogr. Inf. Sci., 2014
Expert Syst. Appl., 2014
2013
Ind. Manag. Data Syst., 2013
Electron. Commer. Res. Appl., 2013
2012
IEICE Trans. Inf. Syst., 2012
Proceedings of the 21st World Wide Web Conference, 2012
2011
24-GOPS 4.5-mm<sup>2</sup> Digital Cellular Neural Network for Rapid Visual Attention in an Object-Recognition SoC.
IEEE Trans. Neural Networks, 2011
Knowl. Based Syst., 2011
Proceedings of the IEEE Ninth International Conference on Dependable, 2011
2010
Visual Image Processing RAM: Memory Architecture With 2-D Data Location Search and Data Consistency Management for a Multicore Object Recognition Processor.
IEEE Trans. Circuits Syst. Video Technol., 2010
Familiarity based unified visual attention model for fast and robust object recognition.
Pattern Recognit., 2010
A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine.
IEEE J. Solid State Circuits, 2010
Proceedings of the 72nd IEEE Vehicular Technology Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
A Configurable Heterogeneous Multicore Architecture With Cellular Neural Network for Real-Time Object Recognition.
IEEE Trans. Circuits Syst. Video Technol., 2009
A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine.
IEEE J. Solid State Circuits, 2009
Memory-centric network-on-chip for power efficient execution of task-level pipeline on a multi-core processor.
IET Comput. Digit. Tech., 2009
A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Proceedings of the 2009 International Conference on Information Networking, 2009
A 118.4GB/s multi-casting network-on-chip for real-time object recognition processor.
Proceedings of the 35th European Solid-State Circuits Conference, 2009
2008
IEEE Commun. Mag., 2008
A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the ESSCIRC 2008, 2008
Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor.
Proceedings of the 45th Design Automation Conference, 2008
2007
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC.
Proceedings of the First International Symposium on Networks-on-Chips, 2007
A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware 2007, 2007
An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
An Integrated Approach to Process-Driven Business Performance Monitoring and Analysis for Real-Time Enterprises.
Proceedings of the Business Intelligence for the Real-Time Enterprises, 2006
2005
A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2002
Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors].
IEEE Trans. Very Large Scale Integr. Syst., 2002
Proceedings of the 39th Design Automation Conference, 2002
2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000