Kwangsoo Han

According to our database, Kwangsoo Han authored at least 17 papers between 2014 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Optimal Generalized H-Tree Topology and Buffering for High-Performance and Low-Power Clock Distribution.

Kwangsoo Han, Andrew B. Kahng, Jiajia Li

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2018

IC Physical Design Methodologies for Advanced Process Nodes

Kwangsoo Han

PhD thesis, 2018

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees.

Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh

Proceedings of the 2018 International Symposium on Physical Design, 2018

A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions.

Kwangsoo Han, Andrew B. Kahng, Christopher Moyes, Alex Zelikovsky

Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018

2017

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts.

Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Benchmarking of Mask Fracturing Heuristics.

Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Performance- and energy-aware optimization of BEOL interconnect stack geometry in advanced technology nodes.

Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI.

Changho Han, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Lutong Wang, Bangqi Xu

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.

Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

Improved performance of 3DIC implementations through inherent awareness of mix-and-match die stacking.

Kwangsoo Han, Andrew B. Kahng, Jiajia Li

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Delay uncertainty and signal criticality driven routing channel optimization for advanced DRAM products.

Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Mulong Luo

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Clock clustering and IO optimization for 3D integration.

Samyoung Bang, Kwangsoo Han, Andrew B. Kahng, Vaishnav Srinivas

Proceedings of the 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, 2015

Scalable Detailed Placement Legalization for Complex Sub-14nm Constraints.

Kwangsoo Han, Andrew B. Kahng, Hyein Lee

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A global-local optimization framework for simultaneous multi-mode multi-corner clock skew variation reduction.

Kwangsoo Han, Jiajia Li, Andrew B. Kahng, Siddhartha Nath, Jongpil Lee

Proceedings of the 52nd Annual Design Automation Conference, 2015

Evaluation of BEOL design rule impacts using an optimal ILP-based detailed router.

Kwangsoo Han, Andrew B. Kahng, Hyein Lee

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Benchmarking of mask fracturing heuristics.

Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng, Emile Sahouria

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

OCV-aware top-level clock tree optimization.

Tuck-Boon Chan, Kwangsoo Han, Andrew B. Kahng, Jae-Gon Lee, Siddhartha Nath

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014