Kwang-Chun Choi

According to our database, Kwang-Chun Choi authored at least 7 papers between 2008 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

A 0.4-V, 90 ∼ 350-MHz PLL With an Active Loop-Filter Charge Pump.

Joung-Wook Moon, Kwang-Chun Choi, Woo-Young Choi

IEEE Trans. Circuits Syst. II Express Briefs, 2014

2013

A 990-µW 1.6-GHz PLL Based on a Novel Supply-Regulated Active-Loop-Filter VCO.

Kwang-Chun Choi, Sung-Geun Kim, Seung-Woo Lee, Bhum-Cheol Lee, Woo-Young Choi

IEEE Trans. Circuits Syst. II Express Briefs, 2013

2012

A Time-to-Digital Converter Based on a Multiphase Reference Clock and a Binary Counter With a Novel Sampling Error Corrector.

Kwang-Chun Choi, Seung-Woo Lee, Bhum-Cheol Lee, Woo-Young Choi

IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 10-Gb/s power and area efficient clock and data recovery circuit in 65-nm CMOS technology.

Jinsoo Rhim, Kwang-Chun Choi, Woo-Young Choi

Proceedings of the International SoC Design Conference, 2012

2010

Demonstration of 60-GHz Link Using a 1.6-Gb/s Mixed-Mode BPSK Demodulator.

Kwang-Chun Choi, Minsu Ko, Duho Kim, Woo-Young Choi

IEICE Trans. Electron., 2010

A 4.8-Gb/s mixed-mode CMOS QPSK demodulator for 60-GHz wireless personal area networks.

Duho Kim, Minsu Ko, Kwang-Chun Choi, Woo-Young Choi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008

A 622-Mb/s Mixed-Mode BPSK Demodulator Using a Half-Rate Bang-Bang Phase Detector.

Duho Kim, Kwang-Chun Choi, Young-Kwang Seo, Hyunchin Kim, Woo-Young Choi

IEEE J. Solid State Circuits, 2008