Kwandong Kim

According to our database, Kwandong Kim authored at least 4 papers between 2019 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE.

Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation.

Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong

IEEE J. Solid State Circuits, 2022

2019

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver.

Moon-Chul Choi, Deog-Kyoon Jeong, Sung-Yong Cho, Minkyo Shim, Byungmin Kim, Han-Gon Ko, Haram Ju, Kwanseo Park, Hyojun Kim, Kwandong Kim

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 512GB 1.1V Managed DRAM Solution with 16GB ODP and Media Controller.

Seong Ju Lee, Byung Deuk Jeon, Kyeong Pil Kang, Dong Yoon Ka, Na Yeon Kim, Yongseop Kim, Yunseok Hong, Mankeun Kang, Jinyong Min, Mingyu Lee, Chunseok Jeong, Kwandong Kim, Doobock Lee, Junghyun Shin, Yuntack Han, Youngbo Shim, Youngjoo Kim, Yongsun Kim, Hyunseok Kim, Jaewoong Yun, Byungsoo Kim, Seokhwan Han, Changwoo Lee, Junyong Song, Ho Uk Song, Il Park, Yongju Kim, Junhyun Chun, Jonghoon Oh

Proceedings of the IEEE International Solid- State Circuits Conference, 2019