Kwan-Weon Kim
According to our database1,
Kwan-Weon Kim
authored at least 12 papers
between 2006 and 2015.
Collaborative distances:
Collaborative distances:
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Bibliography
2015
A 1.2 V 8 Gb 8-Channel 128 GB/s High-Bandwidth Memory (HBM) Stacked DRAM With Effective I/O Test Circuits.
IEEE J. Solid State Circuits, 2015
2014
An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM.
Proceedings of the Symposium on VLSI Circuits, 2014
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2012
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology.
IEEE J. Solid State Circuits, 2012
2011
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Small-area high-accuracy ODT/OCD by calibration of global on-chip for 512M GDDR5 application.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2008
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006