Kusum Lata

Orcid: 0000-0003-3681-2791

Affiliations:
  • LNM Institute of Information Technology, Jaipur, Rajasthan, India


According to our database1, Kusum Lata authored at least 27 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Deep Learning-Based Brain Tumor Detection in Privacy-Preserving Smart Health Care Systems.
IEEE Access, 2024

Exploring Model Poisoning Attack to Convolutional Neural Network Based Brain Tumor Detection Systems.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
FPGA-Based PUF Designs: A Comprehensive Review and Comparative Analysis.
Cryptogr., September, 2023

Enhancing Privacy-Preserving Brain Tumor Detection in Medical Cyber-Physical Systems through Deep Learning Algorithms.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023

2022
Hardware Obfuscation of AES IP Core Using PUFs and PRNG: A Secure Cryptographic Key Generation Solution for Internet-of-Things Applications.
SN Comput. Sci., 2022

Towards the enhancement of AES IP security using hardware obfuscation technique: A practical approach for secure data transmission in IoT.
Secur. Priv., 2022

Hardware obfuscation of AES IP core using combinational hardware Trojan circuit for secure data transmission in IoT applications.
Concurr. Comput. Pract. Exp., 2022

Hardware-Software Co-Design Framework for Data Encryption in Image Processing Systems for the Internet of Things Environment.
IEEE Consumer Electron. Mag., 2022

2021
Hardware Software Co-design framework for Data Encryption in Image Processing Systems for the Internet of Things Environmen.
CoRR, 2021

Reconfigurable HW-SW Co-design Platform for Lung Cancer Detection and Classification.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

Key-based Obfuscation using HT-like Trigger Circuit for 128-bit AES Hardware IP Core.
Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Timing Side-Channel Attack Resistant Key Derivation Functions for Cryptosystems.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020
Design and Analysis of Secure One-way Functions for the Protection of Symmetric Key Cryptosystems.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Hardware Software Co-Simulation of an AES-128 based Data Encryption in Image Processing Systems for the Internet of Things Environment.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

2019
Key-Based Obfuscation Using Strong Physical Unclonable Function: A Secure Implementation.
Proceedings of the Hybrid Intelligent Systems, 2019

2018
Hardware Software Co-Simulation of Obfuscated 128-Bit AES Algorithm for Image Processing Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018

Hardware Implementation of Text Encryption using Elliptic Curve Cryptography over 192 bit Prime Field.
Proceedings of the 2018 International Conference on Advances in Computing, 2018

Enhancing Data Security using Obfuscated 128-bit AES Algorithm - An Active Hardware Obfuscation Approach at RTL Level.
Proceedings of the 2018 International Conference on Advances in Computing, 2018

FPGA Implementation of Traffic Light Controller and its Analysis in the Presence of Hardware Trojan.
Proceedings of the 2018 International Conference on Advances in Computing, 2018

2017
Securing qr codes by rsa on fpga.
Proceedings of the 2017 International Conference on Advances in Computing, 2017

Analysis of aes cryptosystem in the existence of hardware trojan.
Proceedings of the 2017 International Conference on Advances in Computing, 2017

2016
Low-leakage and process-variation-tolerant write-read disturb-free 9T SRA cell using CMOS and FinFETs.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

2013
Formal Verification of Analog and Mixed Signal Designs Using SPICE Circuit Simulation Traces.
J. Electron. Test., 2013

2010
Formal verification of Full-Wave Rectifier using SPICE circuit simulation traces.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Formal verification of tunnel diode oscillator with temperature variations.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Formal Verification of Full-Wave Rectifier: A Case Study
CoRR, 2009

2008
Verification of a MEMS based adaptive cruise control system using simulation and semi-formal approaches.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008


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