Kurt Antreich
Affiliations:- Technical University Munich, Germany
According to our database1,
Kurt Antreich
authored at least 35 papers
between 1987 and 2007.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1994, "For contributions to computer-aided tolerance design of electronic circuits and computer-aided layout design of integrated circuits.".
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Bibliography
2007
Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
2004
Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
2003
Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
2002
Proceedings of the 2002 Design, 2002
Proceedings of the 39th Design Automation Conference, 2002
2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search.
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits.
Proceedings of the 2000 Design, 2000
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs.
ACM Trans. Design Autom. Electr. Syst., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Informationstechnik Tech. Inform., 1999
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints.
Proceedings of the 1999 Design, 1999
1997
Inform. Forsch. Entwickl., 1997
J. Electron. Test., 1997
1995
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
Proceedings of the Proceedings EURO-DAC'95, 1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 32st Conference on Design Automation, 1995
1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
A new power estimation technique with application to decomposition of Boolean functions for low power.
Proceedings of the Proceedings EURO-DAC'94, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits.
Proceedings of the Parallel Computer Architectures: Theory, 1993
Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances.
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1992
Design verification considering manufacturing tolerances by using worst-caste distances.
Proceedings of the conference on European design automation, 1992
1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
1990
Proceedings of the European Design Automation Conference, 1990
1987
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987