Kuninori Kawabata

According to our database, Kuninori Kawabata authored at least 4 papers between 1997 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Development of 16 Mb NRAM Aiming for High Reliability, Small Cell Area, and High Switching Speed.

Hitoshi Saito, Jun'ichi Watanabe, J. Seino, Tetsuro Tamura, Naoya Sashida, Kota Hara, Kuninori Kawabata, Atsushi Fujii, Jun Ohno, Atsushi Nakakubo, Manabu Kojima, T. Shimoyama, H. Wada, Lee Cleveland, H. Luan, R. Sen, N. Leong, T. Gallagher, Thomas Rueckes

Proceedings of the IEEE International Memory Workshop, 2021

2015

An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology.

Shoichiro Kawashima, Keizo Morita, Mitsuharu Nakazawa, Kazuaki Yamane, Mitsuhiro Ogai, Kuninori Kawabata, Kazuaki Takai, Yasuhiro Fujii, Ryoji Yasuda, Wensheng Wang, Yukinobu Hikosaka, Ken'ichi Inoue

IEICE Trans. Electron., 2015

1998

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted 2.1-V word line.

Satoshi Eto, Masato Matsumiya, Masato Takita, Yuki Ishii, Toshikazu Nakamura, Kuninori Kawabata, Hideki Kano, Ayako Kitamoto, Toshimi Ikeda, Toru Koga, Mitsuhiro Higashiho, Yuji Serizawa, Kazuo Itabashi, Osamu Tsuboi, Yuji Yokoyama, Masao Taguchi

IEEE J. Solid State Circuits, 1998

1997

A 256-Mb SDRAM using a register-controlled digital DLL.

Atsushi Hatakeyama, Hirohiko Mochizuki, Tadao Aikawa, Masato Takita, Yuki Ishii, Hironobu Tsuboi, Shin-ya Fujioka, Shusaku Yamaguchi, Makoto Koga, Yuji Serizawa, Koichi Nishimura, Kuninori Kawabata, Yoshinori Okajima, Michiari Kawano, Hideyuki Kojima, Kazuhiro Mizutani, Toru Anezaki, Masatomo Hasegawa, Masao Taguchi

IEEE J. Solid State Circuits, 1997