Kunihiro Asada
Orcid: 0000-0002-1150-0241
According to our database1,
Kunihiro Asada
authored at least 205 papers
between 1992 and 2022.
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Bibliography
2022
4-Cycle-Start-Up Reference-Clock-Less Digital CDR Utilizing TDC-Based Initial Frequency Error Detection with Frequency Tracking Loop.
IEICE Trans. Electron., October, 2022
2021
Shock-wave Transceiver Integration for Mm-wave Active Sensing Applications : Invited Paper.
Proceedings of the International Conference on IC Design and Technology, 2021
2019
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Fault Detection of VLSI Power Supply Network Based on Current Estimation From Surface Magnetic Field.
IEEE Trans. Instrum. Meas., 2019
Spatial resolution improvement for point light source detection in scintillator cube using SPAD array with multi pinholes.
IEICE Electron. Express, 2019
2018
Noninvasive Localization of IGBT Faults by High-Sensitivity Magnetic Probe With RF Stimulation.
IEEE Trans. Instrum. Meas., 2018
IEICE Trans. Electron., 2018
IEICE Trans. Electron., 2018
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
IEICE Electron. Express, 2018
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment.
J. Electron. Test., 2018
A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
2017
IEICE Trans. Electron., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
A CMOS Broadband Transceiver with On-Chip Antenna Array and Built-In Pulse-Delay Calibration for Millimeter-Wave Imaging Applications.
IEICE Trans. Electron., 2017
Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Impulse signal generator based on current-mode excitation and transmission line resonator.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017
A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Extension of power supply impedance emulation method on ATE for multiple power domain.
Proceedings of the 22nd IEEE European Test Symposium, 2017
Proceedings of the Computational Imaging XV, Burlingame, 2017
A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors.
J. Circuits Syst. Comput., 2016
An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface.
IEICE Trans. Electron., 2016
Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing.
IEICE Trans. Electron., 2016
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing.
J. Electron. Test., 2016
A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board.
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Experimental demonstration of stochastic comparators for fine resolution ADC without calibration.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 11th European Workshop on Microelectronics Education, 2016
A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A Near-Field Magnetic Sensing System With High-Spatial Resolution and Application for Security of Cryptographic LSIs.
IEEE Trans. Instrum. Meas., 2015
IEICE Trans. Electron., 2015
Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline.
IEICE Electron. Express, 2015
Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator.
Proceedings of the Nordic Circuits and Systems Conference, 2015
An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
A calibration-free time difference accumulator using two pulses propagating on a single buffer ring.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
Proceedings of the IEEE Sensors Applications Symposium, 2014
Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills.
Proceedings of the 2014 International Test Conference, 2014
A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
2013
IEICE Trans. Electron., 2013
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Self Synchronous Circuits for Robust Operation in Low Voltage and Soft Error Prone Environments.
IEICE Trans. Electron., 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection.
Proceedings of the International Symposium on Physical Design, 2013
Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
A true 4-cycle lock reference-less all-digital burst-mode CDR utilizing coarse-fine phase generator with embedded TDC.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter.
IEICE Trans. Electron., 2012
Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme.
IEICE Trans. Electron., 2012
On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction.
IEICE Trans. Electron., 2012
A 580 fs-Resolution Time-to-Digital Converter Utilizing Differential Pulse-Shrinking Buffer Ring in 0.18 µm CMOS Technology.
IEICE Trans. Electron., 2012
All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator.
IEICE Trans. Electron., 2012
Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling.
IEICE Trans. Electron., 2012
All-Digital Wireless Transceiver with Sub-Sampling Demodulation and Burst-Error Correction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
IEICE Electron. Express, 2012
Power integrity control of ATE for emulating power supply fluctuations on customer environment.
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the International Symposium on Communications and Information Technologies, 2012
Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation.
Proceedings of the 2012 IEEE Symposium on Low-Power and High-Speed Chips, 2012
7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2011
A 65 nm Gate-Level Pipelined Self-Synchronous FPGA for High Performance and Variation Robust Operation.
IEEE J. Solid State Circuits, 2011
Timing-Aware Cell Layout Regularity Enhancement for Reduction of Systematic Gate Critical Dimension Variation.
J. Next Gener. Inf. Technol., 2011
IEICE Trans. Electron., 2011
Variable Length Coded Address Compression for High-Speed 3-D Range-Finder Using Light-Section Method.
IEICE Trans. Electron., 2011
1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells.
IEICE Trans. Electron., 2011
On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch.
IEICE Trans. Electron., 2011
A 65-nm CMOS Fully Integrated Shock-Wave Antenna Array with On-Chip Jitter and Pulse-Delay Adjustment for Millimeter-Wave Active Imaging Application.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
A 0.25-µm Si-Ge Fully Integrated Pulse Transmitter with On-Chip Loop Antenna Array towards Beam-Formability for Millimeter-Wave Active Imaging.
IEICE Trans. Electron., 2011
A 0.18-µm CMOS X-Band Shock Wave Generator with an On-Chip Dipole Antenna and a Digitally Programmable Delay Circuit for Pulse Beam-Formability.
IEICE Trans. Electron., 2011
All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter.
IEICE Trans. Electron., 2011
A High Speed IC Truly Random Number Generator Based on Chaotic Sampling of Regular Waveform.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011
IEICE Electron. Express, 2011
Application of a continuous-time level crossing quantization method for timing noise measurements.
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the International SoC Design Conference, 2011
Energy minimum operation in a reconfigurable gate-level pipelined and power-gated self synchronous FPGA.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Gate-level autonomous watchdog circuit for error robustness based on a 65nm self synchronous system.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
A high frequency resolution Digitally-Controlled Oscillator using single-period switching scheme.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
IEICE Trans. Electron., 2010
A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Electron. Express, 2010
A 256×256 14k range maps/s 3-D range-finding image sensor using row-parallel embedded binary.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Time-to-digital converter based on time difference amplifier with non-linearity calibration.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Self-Synchrounous Circuits with Completion/Error Detection as a Candidate of Future LSI Resilient for PVT Variations and Aging.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability.
IEICE Trans. Electron., 2009
Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links.
Proceedings of the 14th IEEE European Test Symposium, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2007
Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Process Variation Aware Comprehensive Layout Synthesis for Yield Enhancement in Nano-meter CMOS.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Datapath Delay Distributions for Data/Instruction against PVT Variations in 90nm CMOS.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
Analysis of Noise Margins Due to Device Parameter Variations in Sub-100nm CMOS Technology.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
LSI Design Flow for Shot Reduction of Character Projection Electron Beam Direct Writing Using Combined Cell Stencil.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
High-Speed 3-D Measurement System Using Smart Image Sensor and FPGA Based 3-D Engine.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Statistical Model for Logic Errors in CMOS Digital Circuits for Reliability-Driven Design Flow.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Timing-driven cell layout de-compaction for yield optimization by critical area minimization.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
A 375 × 365 high-speed 3-D range-finding image sensor using row-parallel search architecture and multisampling technique.
IEEE J. Solid State Circuits, 2005
IEICE Trans. Electron., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
A Performance Driven Module Generator for a Dual-Rail PLA with Embedded 2-Input Logic Cells.
IEICE Trans. Inf. Syst., 2005
Real-time 3-D measurement system based on light-section method using smart image sensor.
Proceedings of the 2005 International Conference on Image Processing, 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Proceedings of the 31st European Solid-State Circuits Conference, 2005
2004
Design and implementation of real-time 3-D image sensor with 640 × 480 pixel resolution.
IEEE J. Solid State Circuits, 2004
A high-speed and low-voltage associative co-processor with exact Hamming/Manhattan-distance estimation using word-parallel and hierarchical search architecture.
IEEE J. Solid State Circuits, 2004
A 120×110 position sensor with the capability of sensitive and selective light detection in wide dynamic range for robust active range finding.
IEEE J. Solid State Circuits, 2004
Smart Access Image Sensors for High-Speed and High-Resolution 3-D Measurement based on Light-Section Method.
Intell. Autom. Soft Comput., 2004
Exact Wiring Fault Minimization via Comprehensive Layout Synthesis for CMOS Logic Cells.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
A word-parallel digital associative engine with wide search range based on Manhattan distance.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
High-speed position detector using new row-parallel architecture for fast collision prevention system.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
A high-speed logic circuit family with interdigitated array structure for deep sub-micron IC design.
Proceedings of the ESSCIRC 2003, 2003
A smart image sensor with high-speed feeble ID-beacon detection for augmented reality system.
Proceedings of the ESSCIRC 2003, 2003
A high-speed and low-voltage associative co-processor with Hamming distance ordering using word-parallel and hierarchical search architecture.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme.
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
A system level memory power optimization technique using multiple supply and threshold voltages.
Proceedings of ASP-DAC 2001, 2001
2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Proceedings of the Field-Programmable Logic and Applications, 2000
A binary image sensor with flexible motion vector detection using block matching method.
Proceedings of ASP-DAC 2000, 2000
1999
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1998
One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects.
VLSI Design, 1998
An Analysis on VLSI Interconnection Considering Skin Effect.
Proceedings of the ASP-DAC '98, 1998
Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture.
Proceedings of the ASP-DAC '98, 1998
1997
Crosstalk noise in high density and high speed interconnections due to inductive coupling.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1995
Design Methodology for Low Power Data Compressors Based on a Window Detector in a 54X54 Bit Multiplier.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
1992
A general and efficient mask pattern generator for non-series-parallel CMOS transistor network.
Proceedings of the Synthesis for Control Dominated Circuits, 1992