Kunhyuk Kang
According to our database1,
Kunhyuk Kang
authored at least 22 papers
between 2005 and 2010.
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Bibliography
2010
On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Fast and accurate estimation of SRAM read and hold failure probability using critical point sampling.
IET Circuits Devices Syst., 2010
2009
Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Des. Test Comput., 2009
2008
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Device-Aware Yield-Centric Dual-V<sub>t</sub> Design Under Parameter Variations in Nanoscale Technologies.
IEEE Trans. Very Large Scale Integr. Syst., 2007
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ.
Proceedings of the 2007 IEEE International Test Conference, 2007
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.
Proceedings of the 44th Design Automation Conference, 2007
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.
Proceedings of the 44th Design Automation Conference, 2007
2006
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.
ACM Trans. Design Autom. Electr. Syst., 2006
Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Effectiveness of low power dual-V<sub>t</sub> designs in nano-scale technologies under process parameter variations.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 Design, 2005
Fast and accurate estimation of nano-scaled SRAM read failure probability using critical point sampling.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005