Kundan Nepal

Orcid: 0000-0002-4215-3393

According to our database¹, Kundan Nepal authored at least 41 papers between 2004 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

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Links

On csauthors.net:

Bibliography

2024

Dual Use Circuitry for Early Failure Warning and Test.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023

Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift.

[BibT_eX]

[DOI]

J. Electron. Test., April, 2023

Harvesting Wasted Clock Cycles for Efficient Online Testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

2022

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis.

[BibT_eX]

[DOI]

Int. J. Parallel Emergent Distributed Syst., 2022

2021

3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2021

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

2020

Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications.

[BibT_eX]

[DOI]

Proceedings of the 10th Annual Computing and Communication Workshop and Conference, 2020

2019

True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors.

[BibT_eX]

[DOI]

Daniel Hellkamp

Kundan Nepal

J. Circuits Syst. Comput., 2019

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Test Architecture for Fine Grained Capture Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Low-cost instrumentation of high-tunnels for a small co-op farm.

[BibT_eX]

[DOI]

Proceedings of the IEEE Global Humanitarian Technology Conference, 2019

Low cost Brussels sprouts harvester for small farms.

[BibT_eX]

[DOI]

Proceedings of the IEEE Global Humanitarian Technology Conference, 2019

2018

Tools for the 3Cs of Entrepreneurially Minded Learning (EML).

[BibT_eX]

[DOI]

Proceedings of the IEEE Frontiers in Education Conference, 2018

2017

Detecting a trojan die in 3D stacked integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE North Atlantic Test Workshop, 2017

Combinational hardware Trojan detection using logic implications.

[BibT_eX]

[DOI]

Noah Cornell

Kundan Nepal

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Stimulating curiosity and the ability to formulate technical questions in an electric circuits course using the question formulation technique (QFT).

[BibT_eX]

[DOI]

Heath J. LeBlanc

Kundan Nepal

Greg S. Mowry

Proceedings of the 2017 IEEE Frontiers in Education Conference, 2017

2016

Using Existing Reconfigurable Logic in 3D Die Stacks for Test.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

2015

Repairing a 3-D Die-Stack Using Available Programmable Logic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2013

Built-in Self-Repair in a 3D die stack using programmable logic.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

Using implications to choose tests through suspect fault identification.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors.

[BibT_eX]

[DOI]

Kundan Nepal

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

2011

Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults.

[BibT_eX]

[DOI]

Carson Dunbar

Kundan Nepal

J. Comput., 2011

Enhancing online error detection through area-efficient multi-site implications.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Wow! linear systems and signal processing is fun!

[BibT_eX]

[DOI]

Maurice F. Aburdene

Kundan Nepal

Proceedings of the 2011 Frontiers in Education Conference, 2011

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

2010

A Cost Effective Approach for Online Error Detection Using Invariant Relationships.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Improving the testability and reliability of sequential circuits with invariant logic.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Compacting test vector sets via strategic use of implications.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Detecting errors using multi-cycle invariance information.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Using Implications for Online Error Detection.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Designing Nanoscale Logic Circuits Based on Markov Random Fields.

[BibT_eX]

[DOI]

J. Electron. Test., 2007

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Timing analysis for full-custom circuits using symbolic DC formulations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits.

[BibT_eX]

[DOI]

IEEE Micro, 2006

Optimizing noise-immune nanoscale circuits using principles of Markov random fields.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Designing MRF based error correcting circuits for memory elements.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Designing logic circuits for probabilistic computation in the presence of noise.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

Design evolution of the Trinity College IGVC robot ALVIN.

[BibT_eX]

[DOI]

Michelle Bovard

Matthew Gillette

Trishan R. de Lanerolle

J. Field Robotics, 2004

RESTA: a robust and extendable symbolic timing analysis tool.

[BibT_eX]

[DOI]

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Kundan Nepal

Timeline

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On csauthors.net:

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