Kunal P. Ganeshpure

ACM Trans. Design Autom. Electr. Syst., 2014

2013

Game theoretic approach for run-time task scheduling on an multi-processor system on chip.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2013

On runtime task graph extraction in MPSoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

2012

Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip.

[BibT_eX]

[DOI]

Sudarshan Srinivasan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

A DFT Methodology for Repairing Embedded Memories of Large MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011

Maximizing hotspot temperature: Wavelet based modelling of heating and cooling profile of functional workloads.

[BibT_eX]

[DOI]

Sudarshan Srinivasan

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Task model for on-chip communication infrastructure design for multicore systems.

[BibT_eX]

[DOI]

Bharath Phanibhushana

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

On ATPG for Multiple Aggressor Crosstalk Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

An Improved Soft-Error Rate Measurement Technique.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Reducing temperature variability by routing heat pipes.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

On Composite Leakage Current Maximization.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

2007

On ATPG for multiple aggressor crosstalk faults in presence of gate delays.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

On Accelerating Soft-Error Detection by Targeted Pattern Generation.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A Study on Impact of Leakage Current on Dynamic Power.

[BibT_eX]

[DOI]

Ashesh Rastogi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Accelerating Soft Error Rate Testing Through Pattern Selection.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

A Pattern Generation Technique for Maximizing Power Supply Currents.

[BibT_eX]

[DOI]