Kunal Godbole

According to our database, Kunal Godbole authored at least 4 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A 28-nm 75-fs_rms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction.

Wanghua Wu, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho

IEEE J. Solid State Circuits, 2019

2017

A 14-nm 0.14-ps_rms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration.

Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho

IEEE J. Solid State Circuits, 2017

24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs.

Chih-Wei Yao, Wing Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2011

A 65nm CMOS SoC with embedded HSDPA/EDGE transceiver, digital baseband and multimedia processor.

Alberto Cicalini, Sankaran Aniruddhan, Rahul Apte, Frederic Bossu, Ojas Choksi, Dan Filipovic, Kunal Godbole, Tsai-Pi Hung, Christos Komninakis, David Maldonado, Chiewcharn Narathong, Babak Nejati, Deirdre O'Shea, Xiaohong Quan, Raj Rangarajan, Janakiram Sankaranarayanan, Andrew See, Ravi Sridhara, Bo Sun, Wenjun Su, Klaas van Zalinge, Gang Zhang, Kamal Sahota

Proceedings of the IEEE International Solid-State Circuits Conference, 2011