Kun-Hsien Lin

Orcid: 0009-0001-6415-1786

According to our database1, Kun-Hsien Lin authored at least 14 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Applications of AI in Digital Governance Services for Local Taxes- a case of the Local Tax Bureau of Taichung City Government.
Proceedings of the 25th Annual International Conference on Digital Government Research, 2024

2022
A Novel Beam Alignment Scheme for Mobile Millimeter-Wave Communications Based on Compressed Sensing Aided-Kalman Filter.
IEEE Open J. Commun. Soc., 2022

2021
Using Pixel-per-bit Neural Network for Two Rolling Shutter Patterns Decoding in Optical Camera Communication (OCC).
Proceedings of the 30th Wireless and Optical Communications Conference, 2021

Using Machine Learning and Light Spatial Sequence Arrangement for Copying Positioning Unit Cell to Reduce Training Burden in Visible Light Positioning (VLP).
Proceedings of the 30th Wireless and Optical Communications Conference, 2021

Using DIALux and Regression-based Machine Learning Algorithm for Designing Indoor Visible Light Positioning (VLP) and Reducing Training Data Collection.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

2020
Enabling Techniques for Optical Wireless Communication Systems.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

2006
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations.
IEEE Trans. Circuits Syst. I Regul. Pap., 2006

Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board.
Microelectron. Reliab., 2006

2005
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology.
IEEE J. Solid State Circuits, 2005

The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs.
IEEE J. Solid State Circuits, 2005

MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process.
IEICE Trans. Electron., 2005

ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Design on ESD protection scheme for IC with power-down-mode operation.
IEEE J. Solid State Circuits, 2004

ESD protection design for IC with power-down-mode operation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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