Kuen-Wey Lin

According to our database, Kuen-Wey Lin authored at least 8 papers between 2010 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction.

Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin

ACM Trans. Design Autom. Electr. Syst., 2018

Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties.

Kuen-Wey Lin, Masanori Hashimoto, Yih-Lang Li

Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

2017

Near-future traffic evaluation based navigation for automated driving vehicles.

Kuen-Wey Lin, Yih-Lang Li, Masanori Hashimoto

Proceedings of the IEEE Intelligent Vehicles Symposium, 2017

A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points.

Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

Multiple-patterning lithography-aware routing for standard cell layout synthesis.

Kuen-Wey Lin, Yih-Lang Li, Rung-Bin Lin

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2014

Logic block and design methodology for via-configurable structured ASIC using dual supply voltages.

Ta-Kai Lin, Kuen-Wey Lin, Chang-Hao Chiu, Rung-Bin Lin

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2010

Via configurable three-input lookup-tables for structured ASICs.

Yu-Chen Chen, Hou-Yu Pang, Kuen-Wey Lin, Rung-Bin Lin, Hui-Hsiang Tung, Shih-Chieh Su

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Power gating design for standard-cell-like structured ASICs.

Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin

Proceedings of the Design, Automation and Test in Europe, 2010