Kuei-Ann Wen

Orcid: 0000-0002-5742-0730

Affiliations:
  • National Chiao-Tung University, Taiwan


According to our database1, Kuei-Ann Wen authored at least 48 papers between 1990 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Energy-Efficient Sparse FFT and Compressed Transpose Memory for mmWave FMCW Radar Sensor System.
IEEE Trans. Instrum. Meas., 2024

2022
SoC Design for Mobile Real-time Badminton Stroke Classification Design.
Proceedings of the 19th International SoC Design Conference, 2022

The Assessments of Jumping Movement Quality and Control by Using IMU and Its Clinical Applications.
Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022

IMU-Based Real Time Four Type Gait Analysis and Classification and Circuit Implementation.
Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022

2021
IMU-Based Real-Time Jump Height Estimation with DSP and Chip Implementation.
Proceedings of the International Conference on IC Design and Technology, 2021

2017
A low power reconfigurable SAR ADC for CMOS MEMS sensor.
Proceedings of the International SoC Design Conference, 2017

2016
MEMS resonator based thermometer SoC design in CMOS 0.18 μm standard process.
Proceedings of the International SoC Design Conference, 2016

Monolithic MEMS resonator based pressure sensor and readout design.
Proceedings of the International SoC Design Conference, 2016

A decouple structured gyroscope with integrated readout circuit on standard 0.18pm 1P6M CMOS technology.
Proceedings of the International SoC Design Conference, 2016

2013
A monolithic CMOS/MEMS accelerometer with zero-g calibration readout circuit.
Proceedings of Eurocon 2013, 2013

Embedded fully self-biased switched-capacitor for energy and area-efficient cholesteric LCD drivers.
Proceedings of the ESSCIRC 2013, 2013

2012
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter.
IEEE J. Solid State Circuits, 2012

2011
A monolithic CMOS MEMS accelerometer with chopper correlated double sampling readout circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An active guarding technique for substrate noise suppression on LC-tank oscillators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A Design of CMOS Class-E Power Amplifier with Phase Correction for Envelope Elimination and Restoration (EER)/Polar Systems.
IEICE Trans. Electron., 2010

Tri-band CMOS Class-E power amplifier design with phase compensations for polar systems.
Proceedings of the 23rd Canadian Conference on Electrical and Computer Engineering, 2010

2009
A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A Design of 2.6 GHz Auto-Biasing Cascode Class-E PA with Vdd/AM and Vdd /PM Compensations in EER System.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009

2008
Low Complexity and High Performance Equalizer Design for UWB.
Proceedings of the WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008, 2008

A fast settling and low reference spur PLL with double sampling phase detector.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006
Crosstalk-insensitive via-programming ROMs using content-aware design framework.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A full code-patterns coverage high-speed embedded ROM using dynamic virtual guardian technique.
IEEE J. Solid State Circuits, 2006

Strategy of packet detection for burst-mode OFDM systems.
IEICE Electron. Express, 2006

A CMOS distributed amplifier with current reuse optimization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Guest Editorial: System-on-a-Chip for Multimedia Systems.
J. VLSI Signal Process., 2005

Power and Substrate Noise Tolerance of Configurable Embedded Memories in SoC.
J. VLSI Signal Process., 2005

CORDIC-based architecture with channel state information for OFDM baseband receiver.
IEEE Trans. Consumer Electron., 2005

A CMOS Low-Noise Amplifier for Ultra Wideband Wireless Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Dual-Band Mixer Design.
IEICE Trans. Electron., 2005

Via-programmable read-only memory design for full code coverage using a dynamic bit-line shielding technique.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

A low power CMOS low noise amplifier for ultra-wideband wireless applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A low power CMOS wideband variable gain amplifier.
Proceedings of the Second IASTED International Conference on Circuits, 2004

2002
Low-power adaptive pseudo noise code acquisition for spread-spectrum systems.
IEEE Trans. Wirel. Commun., 2002

2001
A programmable pipelined digital differential matched filter for DSSS receiver.
IEEE J. Sel. Areas Commun., 2001

A low-complexity 3-stage parallel interference cancellation receiver (LCPIC) for DS-CDMA cellular systems.
Proceedings of the 54th IEEE Vehicular Technology Conference, 2001

2000
Three-dimensional PAC video codec for wireless data transmission.
IEEE Trans. Circuits Syst. Video Technol., 2000

Spatial/temporal decimation on 3DPAC for very low bit rate video transmission.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
PAC coding for real-time video transmission over mobile radio environment.
Proceedings of the 1999 IEEE Wireless Communications and Networking Conference, 1999

1998
On the design of selective coefficient DCT module.
IEEE Trans. Circuits Syst. Video Technol., 1998

Three-dimensional regression polynomial coding for video transmission.
Proceedings of the 9th IEEE International Symposium on Personal, 1998

1997
Polynomial Approximation Coding for Progressive Image Transmission.
J. Vis. Commun. Image Represent., 1997

1996
A systematic design of protocol processors.
Proceedings of the 7th IEEE International Symposium on Personal, 1996

1995
The transform image codec based on fuzzy control and human visual system.
IEEE Trans. Fuzzy Syst., 1995

1994
VLSI Design of Digital Cellular Neural Networks for Image Processing.
J. Vis. Commun. Image Represent., 1994

1993
Single Processor Design for 2-D Wiener Filter.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

VLSI design of the shuffle-exchange network for 2D fast transforms.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1990
A new transform algorithm for Viterbi decoding.
IEEE Trans. Commun., 1990


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