Kubilay Atasu

According to our database, Kubilay Atasu authored at least 47 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2024

Graph Feature Preprocessor: Real-time Extraction of Subgraph-based Features from Transaction Graphs.

Jovan Blanusa, Maximo Cravero Baraja, Andreea Anghel, Luc von Niederhäusern, Erik R. Altman, Haris Pozidis, Kubilay Atasu

CoRR, 2024

Provably Powerful Graph Neural Networks for Directed Multigraphs.

Béni Egressy, Luc von Niederhäusern, Jovan Blanusa, Erik R. Altman, Roger Wattenhofer, Kubilay Atasu

Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024

2023

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles.

Jovan Blanusa, Kubilay Atasu, Paolo Ienne

ACM Trans. Parallel Comput., September, 2023

Realistic Synthetic Financial Transactions for Anti-Money Laundering Models.

Erik R. Altman, Béni Egressy, Jovan Blanusa, Kubilay Atasu

CoRR, 2023

Realistic Synthetic Financial Transactions for Anti-Money Laundering Models.

Erik R. Altman, Jovan Blanusa, Luc von Niederhäusern, Beni Egressy, Andreea Anghel, Kubilay Atasu

Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

2022

Scalable Fine-Grained Parallel Cycle Enumeration Algorithms.

Jovan Blanusa, Paolo Ienne, Kubilay Atasu

Proceedings of the SPAA '22: 34th ACM Symposium on Parallelism in Algorithms and Architectures, Philadelphia, PA, USA, July 11, 2022

2020

Many-Core Clique Enumeration with Fast Set Intersections.

Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu

Proc. VLDB Endow., 2020

Tera-scale coordinate descent on GPUs.

Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis

Future Gener. Comput. Syst., 2020

Parallelizing Maximal Clique Enumeration on Modern Manycore Processors.

Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

2019

Addressing Interpretability and Cold-Start in Matrix Factorization for Recommender Systems.

Michail Vlachos, Celestine Dünner, Reinhard Heckel, Vassilios G. Vassiliadis, Thomas P. Parnell, Kubilay Atasu

IEEE Trans. Knowl. Data Eng., 2019

Linear-Complexity Data-Parallel Earth Mover's Distance Approximations.

Kubilay Atasu, Thomas Mittelholzer

Proceedings of the 36th International Conference on Machine Learning, 2019

2018

A hardware compilation framework for text analytics queries.

Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee

J. Parallel Distributed Comput., 2018

Faster Text Similarity Using a Linear-Complexity Relaxed Word Mover's Distance.

Kubilay Atasu, Vasileios Vasileiadis, Michail Vlachos

ERCIM News, 2018

Low-Complexity Data-Parallel Earth Mover's Distance Approximations.

Kubilay Atasu, Thomas Mittelholzer

CoRR, 2018

2017

Foreword to the Special Section on Reconfigurable Computing.

Steven Derrien, Kubilay Atasu, João M. P. Cardoso, Jürgen Becker

J. Signal Process. Syst., 2017

Large-Scale Stochastic Learning Using GPUs.

Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haris Pozidis

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

High-Performance Recommender System Training Using Co-Clustering on CPU/GPU Clusters.

Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Michail Vlachos, Haralampos Pozidis

Proceedings of the 46th International Conference on Parallel Processing, 2017

Understanding and optimizing the performance of distributed machine learning applications on apache spark.

Celestine Dünner, Thomas P. Parnell, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis

Proceedings of the 2017 IEEE International Conference on Big Data (IEEE BigData 2017), 2017

Linear-complexity relaxed word Mover's distance with GPU acceleration.

Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Manolis Sifalakis, Haralampos Pozidis, Vasileios Vasileiadis, Michail Vlachos, Cesar Berrospi, Abdel Labbi

Proceedings of the 2017 IEEE International Conference on Big Data (IEEE BigData 2017), 2017

2016

Feature-rich Regular Expression Matching Accelerator for Text Analytics.

Kubilay Atasu

J. Signal Process. Syst., 2016

High-Performance Distributed Machine Learning using Apache SPARK.

Celestine Dünner, Thomas P. Parnell, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis

CoRR, 2016

Annotation-based finite-state transducers on reconfigurable devices.

Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Leftmost longest regular expression matching in reconfigurable logic.

Kubilay Atasu

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

2014

Guest Editorial: Application Specific Processors and Architectures.

Melissa C. Smith, Kubilay Atasu

J. Signal Process. Syst., 2014

Giving Text Analytics a Boost.

Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Huaiyu Zhu, Eva Sitaridi

IEEE Micro, 2014

Hardware-accelerated text analytics.

Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

Compiling text analytics queries to FPGAs.

Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Resource-efficient regular expression matching architecture for text analytics.

Kubilay Atasu

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013

Exploring the design space of programmable regular expression matching accelerators.

Kubilay Atasu, Raphael Polig, Jonathan Rohrer, Christoph Hagleitner

J. Syst. Archit., 2013

Hardware-Accelerated Regular Expression Matching with Overlap Handling on IBM PowerEN Processor.

Kubilay Atasu, Florian Dörfler, Jan van Lunteren, Christoph Hagleitner

Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013

Token-based dictionary pattern matching for text analytics.

Raphael Polig, Kubilay Atasu, Christoph Hagleitner

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Hardware-accelerated regular expression matching for high-throughput text analytics.

Kubilay Atasu, Raphael Polig, Christoph Hagleitner, Frederick R. Reiss

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis.

Joseph Reddington, Kubilay Atasu

IEEE Trans. Very Large Scale Integr. Syst., 2012

FISH: Fast Instruction SyntHesis for Custom Processors.

Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar

IEEE Trans. Very Large Scale Integr. Syst., 2012

Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator.

Jan van Lunteren, Christoph Hagleitner, Timothy Heil, Giora Biran, Uzi Shvadron, Kubilay Atasu

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Proving correctness of regular expression accelerators.

Mitra Purandare, Kubilay Atasu, Christoph Hagleitner

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2009

Memory-efficient distribution of regular expressions for fast deep packet inspection.

Jonathan Rohrer, Kubilay Atasu, Jan van Lunteren, Christoph Hagleitner

Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008

CHIPS: Custom Hardware Instruction Processor Synthesis.

Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fast custom instruction identification by convex subgraph enumeration.

Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

2007

Hardware/software partitioning for custom instruction processors (Özelleştirilebilir komut kümeli işlemciler için yazılım/donanım bölüştürmesi)

Kubilay Atasu

PhD thesis, 2007

Optimizing instruction-set extensible processors under data bandwidth constraints.

Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Exact and approximate algorithms for the extension of embedded processor instruction sets.

Laura Pozzi, Kubilay Atasu, Paolo Ienne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Towards optimal custom instruction processors.

Wayne Luk, Kubilay Atasu, Robert G. Dimond, Oskar Mencer

Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

2005

An integer linear programming approach for identifying instruction-set extensions.

Kubilay Atasu, Günhan Dündar, Can C. Özturan

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004

Efficient AES implementations for ARM based platforms.

Kubilay Atasu, Luca Breveglieri, Marco Macchetti

Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Introduction of local memory elements in instruction set extensions.

Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt

Proceedings of the 41th Design Automation Conference, 2004

2003

Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints.

Kubilay Atasu, Laura Pozzi, Paolo Ienne

Int. J. Parallel Program., 2003