Kuan-Neng Chen

Orcid: 0000-0003-4316-0007

According to our database1, Kuan-Neng Chen authored at least 38 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2018, "For contributions to 3D integrated circuit and packaging technologies".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm<sup>2</sup>) Single-Crystalline Si on SiO2 by Elevated-Epi.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022
An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Room Temperature Cu-Cu Direct Bonding Using Wetting/Passivation Scheme for 3D Integration and Packaging.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2019
Investigation of Low Temperature Cu Pillar Eutectic Bonding for 3D Chip Stacking Technology.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Low Temperature Cu to Cu Direct Bonding below 150 °C with Au Passivation Layer.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Temperature Cycling Reliability of WOW Bumpless Through Silicon Vias.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Low-Temperature Wafer-Level Metal Bonding with Gold Thin Film at 100 °C.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2017
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes.
IEEE Trans. Biomed. Circuits Syst., 2017

An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Reliability investigation and mechanism analysis for a novel bonding method of flexible substrate in 3D integration.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

The influence of device morphology on wafer-level bonding with polymer-coated layer.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
An ultra-fast temporary bonding and release process based on thin photolysis polymer in 3D integration.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014
2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications.
IEEE Trans. Biomed. Circuits Syst., 2014

Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Energy-efficient configurable discrete wavelet transform for neural sensing applications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Reliability of key technologies in 3D integration.
Microelectron. Reliab., 2013

Through-silicon-via-based double-side integrated microsystem for neural sensing applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

Low temperature (<180 °C) bonding for 3D integration.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Wafer-level Cu-Cu bonding technology.
Microelectron. Reliab., 2012

BCB-to-oxide bonding technology for 3D integration.
Microelectron. Reliab., 2012

Low temperature bonding technology for 3D integration.
Microelectron. Reliab., 2012

On-chip self-calibrated process-temperature sensor for TSV 3D integration.
Proceedings of the IEEE 25th International SOC Conference, 2012

2011
Integration schemes and enabling technologies for three-dimensional integrated circuits.
IET Comput. Digit. Tech., 2011

Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

Cu-based bonding technology for 3D integration applications.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Wafer-level bonding/stacking technology for 3D integration.
Microelectron. Reliab., 2010

Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

Wafer-level 3D integration using hybrid bonding.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2008
Wafer-level 3D integration technology.
IBM J. Res. Dev., 2008

2005
Copper wafer bonding in three-dimensional integration.
PhD thesis, 2005

2004
Technology, performance, and computer-aided design of three-dimensional integrated circuits.
Proceedings of the 2004 International Symposium on Physical Design, 2004

2002
Fabrication Technologies for Three-Dimensional Integrated Circuits (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002


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