Ku He

Constantine Caramanis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2013

Low-energy digital filter design based on controlled timing error acceptance.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

Low-energy signal processing using circuit-level timing-error acceptance.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Modeling and synthesis of quality-energy optimal approximate adders.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.

[BibT_eX]

[DOI]

IEEE Trans. Dependable Secur. Comput., 2011

Controlled timing-error acceptance for low energy IDCT design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2009

Mitigation of intra-array SRAM variability using adaptive voltage architecture.

[BibT_eX]

[DOI]

Ashish Kumar Singh

Constantine Caramanis

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

2007

A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Modeling of PMOS NBTI Effect Considering Temperature Variation.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A power gating scheme for ground bounce reduction during mode transition.

[BibT_eX]

[DOI]