Krzysztof S. Berezowski

According to our database, Krzysztof S. Berezowski authored at least 13 papers between 2001 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

Calibration of RO-based temperature sensors for a toolset for measuring thermal behavior of FPGA devices.

Pawel Weber, Maciej Zagrabski, Bartosz Wojciechowski, Maciej Nikodem, Krzysztof Kepa, Krzysztof S. Berezowski

Microelectron. J., 2014

2013

Fast and accurate thermal modeling and simulation of manycore processors and workloads.

Bartosz Wojciechowski, Krzysztof S. Berezowski, Piotr Patronik, Janusz Biernat

Microelectron. J., 2013

Empirical Recovery of Input Nonlinearity in Distributed Element Models.

Przemyslaw Sliwinski, Krzysztof S. Berezowski, Pawel Wachel, Gilles Sicard, Laurent Fesquet

Proceedings of the 11th IFAC International Workshop on Adaptation and Learning in Control and Signal Processing, 2013

2012

Design of an RNS reverse converter for a new five-moduli special set.

Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011

Identification of Threshold Functions and Synthesis of Threshold Networks.

Tejaswi Gowda, Sarma B. K. Vrudhula, Niranjan Kulkarni, Krzysztof S. Berezowski

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Fast and energy-efficient constant-coefficient FIR filters using residue number system.

Piotr Patronik, Krzysztof S. Berezowski, Stanislaw J. Piestrak, Janusz Biernat, Aviral Shrivastava

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS.

Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Out-of-order issue logic using sorting networks.

Siddhesh S. Mhambrey, Lawrence T. Clark, Satendra Kumar Maurya, Krzysztof S. Berezowski

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2009

Exploiting residue number system for power-efficient digital signal processing in embedded processors.

Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak

Proceedings of the 2009 International Conference on Compilers, 2009

2008

Analytical results for design space exploration of multi-core processors employing thread migration.

Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski

Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

2007

Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices.

Krzysztof S. Berezowski, Sarma B. K. Vrudhula

J. Multiple Valued Log. Soft Comput., 2007

2005

Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series.

Krzysztof S. Berezowski, Sarma B. K. Vrudhula

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2001

Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis.

Krzysztof S. Berezowski

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001