Krzysztof Marcinek

Orcid: 0000-0001-7952-5093

According to our database1, Krzysztof Marcinek authored at least 16 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

Online presence:

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Bibliography

2024
Implementation of Hardware Trace Buffer Module for RISC-V Processor Core.
Proceedings of the 31st International Conference on Mixed Design of Integrated Circuits and System , 2024

2023
Dual TDL Based Phase Difference Detector Architecture.
Proceedings of the 30th International Conference on Mixed Design of Integrated Circuits and System, 2023

2022
Clock Signal Phase Alignment System for Daisy Chained Integrated Circuits.
Proceedings of the 29th International Conference on Mixed Design of Integrated Circuits and System, 2022

2020
GNSS-ISE: Instruction Set Extension for GNSS Baseband Processing.
Sensors, 2020

Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069.
Sensors, 2020

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor.
Sensors, 2020

2019
Configurable MBIST Processor for Embedded Memories Testing.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Implementation and Comparison of SPA and DPA Countermeasures for Elliptic Curve Point Multiplication.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Design and Verification Environment for RISC-V Processor Cores.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Retargeting the MIPS-II CPU Core to the RISC-V Architecture.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

2016
BioSoC: Highly integrated System-on-Chip for health monitoring.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
A CMOS system-on-chip for physiological parameters acquisition, processing and monitoring.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Implementation of the ADELITE Microcontroller for Biomedical Applications.
Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2013
ELEON3LP - Superscalar and low-power enhancements of single issue general purpose processor model.
Microprocess. Microsystems, 2013

2012
AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systems.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2009
Enhanced LEON3 core for superscalar processing.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009


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