Krit Athikulwongse

Orcid: 0000-0002-4092-8634

According to our database1, Krit Athikulwongse authored at least 20 papers between 1997 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2022
Implementation of and Experimentation with Ground-Penetrating Radar for Real-Time Automatic Detection of Buried Improvised Explosive Devices.
Sensors, 2022

2021
Improved Step Detection with Smartphone Handheld Mode Recognition.
Proceedings of the 13th International Conference on Knowledge and Smart Technology, 2021

2020
Mapping the Physical and Dielectric Properties of Layered Soil Using Short-Time Matrix Pencil Method-Based Ground-Penetrating Radar.
IEEE Access, 2020

2019
High Performance Application Specific Stream Architecture for Hardware Acceleration of HOG-SVM on FPGA.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Application Specific Architecture for Hardware Accelerating HOG-SVM to Achieve High Throughput on HD Frames.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2016
Fast bidirectional shortest path on GPU.
IEICE Electron. Express, 2016

2015
Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory).
IEEE Trans. Computers, 2015

2014
Exploiting Die-to-Die Thermal Coupling in 3-D IC Placement.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Exploiting die-to-die thermal coupling in 3D IC placement.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Design for manufacturability and reliability for TSV-based 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2010
Stress-driven 3D-IC placement with TSV keep-out zone and regularity study.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

TSV stress aware timing analysis with applications to 3D-IC layout optimization.
Proceedings of the 47th Design Automation Conference, 2010

Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

Buffered clock tree sizing for skew minimization under power and thermal budgets.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
A study of Through-Silicon-Via impact on the 3D stacked IC layout.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

1997
An NTSC and PAL closed caption processor.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997


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