Krisztián Flautner
Orcid: 0009-0002-8347-1811
According to our database1,
Krisztián Flautner
authored at least 56 papers
between 1999 and 2024.
Collaborative distances:
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Bibliography
2024
Scaling Down to Scale Up: A Cost-Benefit Analysis of Replacing OpenAI's LLM with Open Source SLMs in Production.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024
2023
Scaling Down to Scale Up: A Cost-Benefit Analysis of Replacing OpenAI's GPT-4 with Self-Hosted Open Source SLMs in Production.
CoRR, 2023
The Jaseci Programming Paradigm and Runtime Stack: Building Scale-Out Production Applications Easy and Fast.
IEEE Comput. Archit. Lett., 2023
Proceedings of the Findings of the Association for Computational Linguistics: ACL 2023, 2023
2014
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014
2011
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation".
IEEE J. Solid State Circuits, 2011
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation.
IEEE J. Solid State Circuits, 2011
High-Performance Multiprocessor System on Chip: Trends in Chip Architecture for the Mass Market.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the 46th Design Automation Conference, 2009
2008
ACM Trans. Embed. Comput. Syst., 2008
ACM J. Emerg. Technol. Comput. Syst., 2008
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor.
Proceedings of the Embedded Computer Systems: Architectures, 2008
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
SoC-C: efficient programming abstractions for heterogeneous multicore systems on chip.
Proceedings of the 2008 International Conference on Compilers, 2008
2007
IEEE Micro, 2007
Proceedings of the Embedded Computer Systems: Architectures, 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006
Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006
Cutting across layers of abstraction: : removing obstacles from the advancement of embedded systems.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
PicoServer: using 3D stacking technology to enable a compact energy efficient chip multiprocessor.
Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors.
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
Proceedings of the High Performance Embedded Architectures and Compilers, 2005
Proceedings of the 2005 International Conference on Compilers, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Micro, 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Application-Specific Processing on a General-Purpose Core via Transparent Instruction Set Customization.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003
2002
Proceedings of the 5th Symposium on Operating System Design and Implementation (OSDI 2002), 2002
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002
Proceedings of the 29th International Symposium on Computer Architecture (ISCA 2002), 2002
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
2001
PhD thesis, 2001
Proceedings of the MOBICOM 2001, 2001
2000
Proceedings of the ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, 2000
1999
SIGARCH Comput. Archit. News, 1999