Kristof Denolf

Orcid: 0000-0001-6668-4562

According to our database1, Kristof Denolf authored at least 32 papers between 2000 and 2024.

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Bibliography

2024
CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture.
ACM Trans. Reconfigurable Technol. Syst., September, 2024

Tailor: Altering Skip Connections for Resource-Efficient Inference.
ACM Trans. Reconfigurable Technol. Syst., March, 2024

Error Diffusion: Post Training Quantization with Block-Scaled Number Formats for Neural Networks.
CoRR, 2024

2023
Microscaling Data Formats for Deep Learning.
CoRR, 2023

Tailor: Altering Skip Connections for Resource-Efficient Inference.
CoRR, 2023

SPARTA: Spatial Acceleration for Efficient and Scalable Horizontal Diffusion Weather Stencil Computation.
Proceedings of the 37th International Conference on Supercomputing, 2023

CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

Adapting Skip Connections for Resource-Efficient FPGA Inference.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
A Framework for Designing Efficient Deep Learning-Based Genomic Basecallers.
CoRR, 2022

2021
Benchmarking vision kernels and neural network inference accelerators on embedded platforms.
J. Syst. Archit., 2021

ASLR: An Adaptive Scheduler for Learning Rate.
Proceedings of the International Joint Conference on Neural Networks, 2021

S2N2: A FPGA Accelerator for Streaming Spiking Neural Networks.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Trainable Preprocessing for Reduced Precision Neural Networks.
Proceedings of the 29th European Signal Processing Conference, 2021

2019
Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels.
Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2009
Rate-distortion-complexity performance analysis of the SVC decoder.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

Using C-to-gates to program streaming image processing kernels efficiently on FPGAs.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Cross-layer optimization for multi-user video streaming over IEEE 802.11E HCCA wireless networks.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

2007
A Systematic Approach to Design Low-Power Video Codec Cores.
EURASIP J. Embed. Syst., 2007

Exploiting the Expressiveness of Cyclo-Static Dataflow to Model Multimedia Implementations.
EURASIP J. Adv. Signal Process., 2007

SPRINT: A Tool to Generate Concurrent Transaction-Level Models from Sequential Code.
EURASIP J. Adv. Signal Process., 2007

Modelling Energy Consumption of an ASIC MPEG-4 Simple Profile Encoder.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

2005
Memory Centric Design of an MPEG-4 Video Encoder.
IEEE Trans. Circuits Syst. Video Technol., 2005

Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

A scalable, multi-stream MPEG-4 video decoder for conferencing and surveillance applications.
Proceedings of the 2005 International Conference on Image Processing, 2005

Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2004
Performance and Complexity Co-evaluation of the Advanced Video Coding Standard for Cost-Effective Multimedia Communications.
EURASIP J. Adv. Signal Process., 2004

A Power Optimized Display Memory Organization for Handheld User Terminal.
Proceedings of the 2004 Design, 2004

2002
Algorithmic and architectural co-design of a motion-estimation engine for low-power video devices.
IEEE Trans. Circuits Syst. Video Technol., 2002

Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

2000
Cost-Efficient C-Level Design of an MPEG-4 Video Decoder.
Proceedings of the Integrated Circuit Design, 2000

3D computational graceful degradation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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