Krishnendu Chakrabarty
Orcid: 0000-0003-4475-6435Affiliations:
- Arizona State University, USA
- Duke University, Durham, NC, USA (former)
According to our database1,
Krishnendu Chakrabarty
authored at least 885 papers
between 1993 and 2024.
Collaborative distances:
Collaborative distances:
Awards
ACM Fellow
ACM Fellow 2013, "For contributions to optimization methods for system-on-chip test automation, microfluidic biochips, and sensor network infrastructure.".
IEEE Fellow
IEEE Fellow 2008, "For contributions to the testing of core-based system-on-chip integrated circuits".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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on ee.duke.edu
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on dl.acm.org
On csauthors.net:
Bibliography
2024
DAWN: Efficient Trojan Detection in Analog Circuits Using Circuit Watermarking and Neural Twins.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
ALT-Lock: Logic and Timing Ambiguity-Based IP Obfuscation Against Reverse Engineering.
IEEE Trans. Very Large Scale Integr. Syst., August, 2024
Mitigating Slow-to-Write Errors in Memristor-Mapped Graph Neural Networks Induced by Adversarial Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024
Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration.
IEEE Trans. Very Large Scale Integr. Syst., July, 2024
IEEE Trans. Very Large Scale Integr. Syst., May, 2024
ACM Trans. Design Autom. Electr. Syst., May, 2024
Dynamic Adaptation Using Deep Reinforcement Learning for Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., March, 2024
IEEE Internet Things J., February, 2024
Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., January, 2024
The Unlikely Hero: Nonideality in Analog Photonic Neural Networks as Built-in Defender Against Adversarial Attacks.
CoRR, 2024
SPICED: Syntactical Bug and Trojan Pattern Identification in A/MS Circuits using LLM-Enhanced Detection.
CoRR, 2024
Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
Accelerating Fluid Loading in Sample Preparation with Fully Programmable Valve Arrays.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
ML-TIME: ML-driven Timing Analysis of Integrated Circuits in the Presence of Process Variations and Aging Effects.
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024
Proceedings of the IEEE European Test Symposium, 2024
Proceedings of the IEEE European Test Symposium, 2024
PathDriver-Wash: A Path-Driven Wash Optimization Method for Continuous-Flow Lab-on-a-Chip Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
Proceedings of the Applied Cryptography and Network Security Workshops, 2024
2023
Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
Enhanced Built-In Self-Diagnosis and Self-Repair Techniques for Daisy-Chain Design in MEDA Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023
ESSENCE: Exploiting Structured Stochastic Gradient Pruning for Endurance-Aware ReRAM-Based In-Memory Training Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023
Deep Reinforcement Learning-Based Approach for Efficient and Reliable Droplet Routing on MEDA Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Des. Test, April, 2023
IEEE Trans. Very Large Scale Integr. Syst., March, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023
IEEE Internet Things J., March, 2023
Fusion of IoT, AI, Edge-Fog-Cloud, and Blockchain: Challenges, Solutions, and a Case Study in Healthcare and Medicine.
IEEE Internet Things J., March, 2023
Unsupervised Two-Stage Root-Cause Analysis With Transfer Learning for Integrated Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
IEEE Trans. Emerg. Top. Comput., 2023
Accelerating Graph Neural Network Training on ReRAM-Based PIM Architectures via Graph and Model Pruning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators.
CoRR, 2023
Analysis of Optical Loss and Crosstalk Noise in MZI-based Coherent Photonic Neural Networks.
CoRR, 2023
Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs <sup>*</sup>.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Functional Test Generation for AI Accelerators using Bayesian Optimization<sup>∗</sup>.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the IEEE International Test Conference, 2023
Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs.
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the IEEE International Test Conference, 2023
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023
Proceedings of the IEEE International Conference on Digital Health, 2023
Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning<sup>*</sup>.
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer Obfuscation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2023
Proceedings of the 23rd IEEE/ACM International Symposium on Cluster, 2023
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
IEEE Trans. Biomed. Circuits Syst., December, 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Knowledge Transfer in Board-Level Functional Fault Diagnosis Enabled by Domain Adaptation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Mixing Models as Integer Factorization: A Key to Sample Preparation With Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
High-Throughput Training of Deep CNNs on ReRAM-Based Heterogeneous Architectures via Optimized Normalization Layers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Efficient Regulation of Synthetic Biocircuits Using Droplet-Aliquot Operations on MEDA Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Accurate and Robust Malware Detection: Running XGBoost on Runtime Data From Performance Counters.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Efficient Identification of Critical Faults in Memristor-Based Inferencing Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
A Resilient and Hierarchical IoT-Based Solution for Stress Monitoring in Everyday Settings.
IEEE Internet Things J., 2022
ACM Comput. Surv., 2022
A Framework for Automated Correctness Checking of Biochemical Protocol Realizations on Digital Microfluidic Biochips.
CoRR, 2022
CoRR, 2022
Characterization and Optimization of Integrated Silicon-Photonic Neural Networks under Fabrication-Process Variations.
CoRR, 2022
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
CHAMP: Coherent Hardware-Aware Magnitude Pruning of Integrated Photonic Neural Networks.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022
Proceedings of the IEEE International Test Conference, 2022
Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the 21st IEEE International Conference on Machine Learning and Applications, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
LoCI: An Analysis of the Impact of Optical Loss and Crosstalk Noise in Integrated Silicon-Photonic Neural Networks.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
TaintLock: Preventing IP Theft through Lightweight Dynamic Scan Encryption using Taint Bits<sup>*</sup>.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the IEEE European Test Symposium, 2022
Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2021
IEEE Trans. Inf. Forensics Secur., 2021
ACM Trans. Embed. Comput. Syst., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Toward Hardware-Based IP Vulnerability Detection and Post-Deployment Patching in Systems-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021
Proceedings of the Machine Learning for Healthcare Conference, 2021
A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks<sup>*</sup>.
Proceedings of the IEEE International Test Conference, 2021
Adaptive Methods for Machine Learning-Based Testing of Integrated Circuits and Boards.
Proceedings of the IEEE International Test Conference, 2021
On-line Functional Testing of Memristor-mapped Deep Neural Networks using Backdoored Checksums.
Proceedings of the IEEE International Test Conference, 2021
Efficient Fault-Criticality Analysis for AI Accelerators using a Neural Twin<sup>∗</sup>.
Proceedings of the IEEE International Test Conference, 2021
Proceedings of the IEEE International Test Conference in Asia, 2021
Proceedings of the 38th International Conference on Machine Learning, 2021
Multi-Objective Optimization of ReRAM Crossbars for Robust DNN Inferencing under Stochastic Noise.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Heterogeneous Manycore Architectures Enabled by Processing-in-Memory for Deep Learning: From CNNs to GNNs: (ICCAD Special Session Paper).
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
DARe: DropLayer-Aware Manycore ReRAM architecture for Training Graph Neural Networks.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Efficient Identification of Critical Faults in Memristor Crossbars for Deep Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
ReGraphX: NoC-enabled 3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Securing Biochemical Samples Using Molecular Barcoding on Digital Microfluidic Biochips.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021
2020
Programmable Daisychaining of Microelectrodes to Secure Bioassay IP in MEDA Biochips.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs.
IEEE Trans. Very Large Scale Integr. Syst., 2020
Runtime Identification of Hardware Trojans by Feature Analysis on Gate-Level Unstructured Data and Anomaly Detection.
ACM Trans. Design Autom. Electr. Syst., 2020
ACM Trans. Design Autom. Electr. Syst., 2020
ACM Trans. Design Autom. Electr. Syst., 2020
ACM Trans. Design Autom. Electr. Syst., 2020
ACM Trans. Design Autom. Electr. Syst., 2020
Molecular Barcoding as a Defense Against Benchtop Biochemical Attacks on DNA Fingerprinting and Information Forensics.
IEEE Trans. Inf. Forensics Secur., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Droplet Barcoding in Single-Cell Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Hierarchical Symbol-Based Health-Status Analysis Using Time-Series Data in a Core Router System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Timing-Driven Flow-Channel Network Construction for Continuous-Flow Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
BioCyBig: A Cyberphysical System for Integrative Microfluidics-Driven Analysis of Genomic Association Studies.
IEEE Trans. Big Data, 2020
Sensor-Array Optimization Based on Time-Series Data Analytics for Sanitation-Related Malodor Detection.
IEEE Trans. Biomed. Circuits Syst., 2020
IEEE Trans. Biomed. Circuits Syst., 2020
ACM J. Emerg. Technol. Comput. Syst., 2020
3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks.
ACM J. Emerg. Technol. Comput. Syst., 2020
LSTM-based Analysis of Temporally- and Spatially-Correlated Signatures for Intermittent Fault Detection.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
Proceedings of the IEEE International Test Conference, 2020
Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power Consumption.
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the IEEE International Test Conference, 2020
Adaptive Droplet Routing in Digital Microfluidic Biochips Using Deep Reinforcement Learning.
Proceedings of the 37th International Conference on Machine Learning, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the IEEE European Test Symposium, 2020
Functional-Like Transition Delay Fault Test-Pattern Generation using a Bayesian-Based Circuit Model.
Proceedings of the IEEE European Test Symposium, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image Segmentation.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs <sup>*</sup>.
Proceedings of the 29th IEEE Asian Test Symposium, 2020
Proceedings of the 29th IEEE Asian Test Symposium, 2020
NodeRank: Observation-Point Insertion for Fault Localization in Monolithic 3D ICs<sup>∗</sup>.
Proceedings of the 29th IEEE Asian Test Symposium, 2020
Reliability-Oriented IEEE Std. 1687 Network Design and Block-Aware High-Level Synthesis for MEDA Biochips.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
ACM Trans. Design Autom. Electr. Syst., 2019
ACM Trans. Design Autom. Electr. Syst., 2019
IEEE Trans. Inf. Forensics Secur., 2019
Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization.
ACM Trans. Embed. Comput. Syst., 2019
Fault-Tolerant Training Enabled by On-Line Fault Detection for RRAM-Based Neural Computing Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Predicting X-Sensitivity of Circuit-Inputs on Test-Coverage: A Machine-Learning Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Optimization of Multi-Target Sample Preparation On-Demand With Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
A Design-for-Test Solution Based on Dedicated Test Layers and Test Scheduling for Monolithic 3-D Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Changepoint-Based Anomaly Detection for Prognostic Diagnosis in a Core Router System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Micro-Electrode-Dot-Array Digital Microfluidic Biochips: Technology, Design Automation, and Test Techniques.
IEEE Trans. Biomed. Circuits Syst., 2019
IEEE Des. Test, 2019
IEEE Des. Test, 2019
Emerging Hardware Techniques and EDA Methodologies for Neuromorphic Computing (Dagstuhl Seminar 19152).
Dagstuhl Reports, 2019
Test-Cost Reduction for 2.5D ICs Using Microspring Technology for Die Attachment and Rework.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Black-Box Test-Coverage Analysis and Test-Cost Reduction Based on a Bayesian Network Model.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Reliable Power Delivery and Analysis of Power-Supply Noise During Testing in Monolithic 3D ICs.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Proceedings of the IEEE International Test Conference, 2019
Fault Recovery in Micro-Electrode-Dot-Array Digital Microfluidic Biochips Using an IJTAG NetworkBehaviors.
Proceedings of the IEEE International Test Conference, 2019
Knowledge Transfer in Board-Level Functional Fault Identification using Domain Adaptation.
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the IEEE International Test Conference, 2019
Can Multi-Layer Microfluidic Design Methods Aid Bio-Intellectual Property Protection?
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
The Internet of Microfluidic Things: Perspectives on System Architecture and Design Challenges: Invited Paper.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
REGENT: A Heterogeneous ReRAM/GPU-based Architecture Enabled by NoC for Training CNNs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
BioScan: Parameter-Space Exploration of Synthetic Biocircuits Using MEDA Biochips<sup>∗</sup>.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019
Sensor-Array Optimization Based on Mutual Information for Sanitation-Related Malodor Alerts.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Factorization based dilution of biochemical fluids with micro-electrode-dot-array biochips.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
ACM Trans. Design Autom. Electr. Syst., 2018
Multicast Testing of Interposer-Based 2.5D ICs: Test-Architecture Design and Test Scheduling.
ACM Trans. Design Autom. Electr. Syst., 2018
Demand-Driven Single- and Multitarget Mixture Preparation Using Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., 2018
Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-Chip.
ACM Trans. Design Autom. Electr. Syst., 2018
Adaptive and Roll-Forward Error Recovery in MEDA Biochips Based on Droplet-Aliquot Operations and Predictive Analysis.
IEEE Trans. Multi Scale Comput. Syst., 2018
H<sup>2</sup>OEIN: A Hierarchical Hybrid Optical/Electrical Interconnection Network for Exascale Computing Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring of Run-Time Stress.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array Digital Microfluidic Biochip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Toward Predictive Fault Tolerance in a Core-Router System: Anomaly Detection Using Correlation-Based Time-Series Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Cyber-Physical Digital-Microfluidic Biochips: Bridging the Gap Between Microfluidics and Microbiology.
Proc. IEEE, 2018
J. Electron. Test., 2018
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Proceedings of the 36th IEEE VLSI Test Symposium, 2018
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018
Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism.
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Test Conference, 2018
Proceedings of the IEEE International Test Conference, 2018
Test generation for microfluidic fully programmable valve arrays (FPVAs) with heuristic acceleration.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
Power-Supply Noise Analysis for Monolithic 3D ICs Using Electrical and Thermal Co-Simulation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
An efficient fault-tolerant valve-based microfluidic routing fabric for single-cell analysis.
Proceedings of the 23rd IEEE European Test Symposium, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Fault-tolerant valve-based microfluidic routing fabric for droplet barcoding in single-cell analysis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Pre-assembly testing of interconnects in embedded multi-die interconnect bridge (EMIB) dies.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the Advanced Logic Synthesis, 2018
2017
ACM Trans. Design Autom. Electr. Syst., 2017
Synthesis of Error-Recovery Protocols for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
ACM Trans. Embed. Comput. Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-V<sub>dd</sub> SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Synthesis of Cyberphysical Digital-Microfluidic Biochips for Real-Time Quantitative Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Control-Layer Routing and Control-Pin Minimization for Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Adaptation of Biochemical Protocols to Handle Technology-Change for Digital Microfluidics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Droplet Size-Aware High-Level Synthesis for Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits Syst., 2017
Droplet Size-Aware and Error-Correcting Sample Preparation Using Micro-Electrode-Dot-Array Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits Syst., 2017
Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting 2017-1).
NII Shonan Meet. Rep., 2017
Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits.
ACM J. Emerg. Technol. Comput. Syst., 2017
Offline Error Detection in MEDA-Based Digital Microfluidic Biochips Using Oscillation-Based Testing Methodology.
J. Electron. Test., 2017
IEEE Des. Test, 2017
IEEE Des. Test, 2017
Test-cost optimization in a scan-compression architecture using support-vector regression.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the IEEE International Test Conference, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Adaptive error recovery in MEDA biochips based on droplet-aliquot operations and predictive analysis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Sortex: Efficient timing-driven synthesis of reconfigurable flow-based biochips for scalable single-cell screening.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Digital-microfluidic biochips for quantitative analysis: Bridging the Gap between microfluidics and microbiology.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems.
Proceedings of the 54th Annual Design Automation Conference, 2017
Data analytics enables energy-efficiency and robustness: from mobile to manycores, datacenters, and networks (special session paper).
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017
Proceedings of the 26th IEEE Asian Test Symposium, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Error-Correcting Sample Preparation with Cyberphysical Digital Microfluidic Lab-on-Chip.
ACM Trans. Design Autom. Electr. Syst., 2016
Optimization of 3D Digital Microfluidic Biochips for the Multiplexed Polymerase Chain Reaction.
ACM Trans. Design Autom. Electr. Syst., 2016
IEEE ACM Trans. Comput. Biol. Bioinform., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Wash Optimization and Analysis for Cross-Contamination Removal Under Physical Constraints in Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Fault Diagnosis for Leakage and Blockage Defects in Flow-Based Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
A Distributed, Reconfigurable, and Reusable BIST Infrastructure for Test and Diagnosis of 3-D-Stacked ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip.
IEEE Trans. Computers, 2016
Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3D Small-world Network-on-Chip.
CoRR, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Supply-voltage optimization to account for process variations in high-volume manufacturing testing.
Proceedings of the 2016 IEEE International Test Conference, 2016
Accurate anomaly detection using correlation-based time-series analysis in a core router system.
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Energy-efficient and reliable 3D network-on-chip (NoC): architectures and optimization algorithms.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing.
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Integrated and real-time quantitative analysis using cyberphysical digital-microfluidic biochips.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 2016 International Conference on Compilers, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
Aging- and Variation-Aware Delay Monitoring Using Representative Critical Path Selection.
ACM Trans. Design Autom. Electr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
Layout-Aware Mixture Preparation of Biochemical Fluids on Application-Specific Digital Microfluidic Biochips.
ACM Trans. Design Autom. Electr. Syst., 2015
IEEE Trans. Multi Scale Comput. Syst., 2015
Information-Theoretic Syndrome Evaluation, Statistical Root-Cause Analysis, and Correlation-Based Feature Selection for Guiding Board-Level Fault Diagnosis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip for the Polymerase Chain Reaction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Accurate Predictions of Process-Execution Time and Process Status Based on Support-Vector Regression for Enterprise Information Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Real-Time Production Scheduler for Digital-Print-Service Providers Based on a Dynamic Incremental Evolutionary Algorithm.
IEEE Trans Autom. Sci. Eng., 2015
Waste-aware single-target dilution of a biochemical fluid using digital microfluidic biochips.
Integr., 2015
IEEE Des. Test, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
Proceedings of the Formal Modeling and Verification of Cyber-Physical Systems, 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Efficient observation-point insertion for diagnosability enhancement in digital circuits.
Proceedings of the 2015 IEEE International Test Conference, 2015
A general testing method for digital microfluidic biochips under physical constraints.
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators.
Proceedings of the 2015 IEEE International Test Conference, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT Infrastructure.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Digital Microfluidic Biochips: Towards Functional Diversity, More than Moore, and Cyberphysical Integration.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design.
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
Experimental demonstration of error recovery in an integrated cyberphysical digital-microfluidic platform.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Design and optimization of 3D digital microfluidic biochips for the polymerase chain reaction.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Hardware/Software Co-Design and Optimization for Cyberphysical Integration in Digital Microfluidic Biochips.
Springer, ISBN: 978-3-319-09005-4, 2015
Data-Driven Optimization and Knowledge Discovery for an Enterprise Information System.
Springer, ISBN: 978-3-319-18737-2, 2015
2014
Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Board-Level Functional Fault Diagnosis Using Multikernel Support Vector Machines and Incremental Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Biochemistry Synthesis on a Cyberphysical Digital Microfluidics Platform Under Completion-Time Uncertainties in Fluidic Operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Testing of Flow-Based Microfluidic Biochips: Fault Modeling, Test Generation, and Experimental Demonstration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Biochip Synthesis and Dynamic Error Recovery for Sample Preparation Using Digital Microfluidics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Contactless Pre-Bond TSV Test and Diagnosis Using Ring Oscillators and Multiple Voltage Levels.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-Based Multicore SoCs.
IEEE Trans. Computers, 2014
An Optimal Two-Mixer Dilution Engine with Digital Microfluidics for Low-Power Applications.
J. Low Power Electron., 2014
Theory and analysis of generalized mixing and dilution of biochemical fluids using digital microfluidic biochips.
ACM J. Emerg. Technol. Comput. Syst., 2014
IPSJ Trans. Syst. LSI Des. Methodol., 2014
High-throughput dilution engine for sample preparation on digital microfluidic biochips.
IET Comput. Digit. Tech., 2014
J. Electron. Test., 2014
Information-Theoretic Framework for Evaluating and Guiding Board-Level Functional-Fault Diagnosis.
IEEE Des. Test, 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Test generation and design-for-testability for flow-based mVLSI microfluidic biochips.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014
Tutorial T5: Microfluidic Biochips: Connecting VLSI and Embedded Systems to the Life Sciences.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic Biochip.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Knowledge discovery and knowledge transfer in board-level functional fault diagnosis.
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the 2014 International Test Conference, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Design automation for biochemistry synthesis on a digital microfluidic lab-on-a-chip.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Output-bit selection with X-avoidance using multiple counters for test-response compaction.
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014
Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Demand-Driven Mixture Preparation and Droplet Streaming using Digital Microfluidic Biochips.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 2014 International Conference on Compilers, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
Wash optimization for cross-contamination removal in flow-based microfluidic biochips.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
Springer, ISBN: 978-3-319-02377-9, 2014
Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.
Proceedings of the Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits., 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
ACM Trans. Design Autom. Electr. Syst., 2013
Board-Level Functional Fault Diagnosis Using Artificial Neural Networks, Support-Vector Machines, and Weighted-Majority Voting.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Real-Time Error Recovery in Cyberphysical Digital-Microfluidic Biochips Using a Compact Dictionary.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Detection, Diagnosis, and Recovery From Clock-Domain Crossing Failures in Multiclock SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults.
J. Electron. Test., 2013
CoRR, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 31st IEEE VLSI Test Symposium, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
On-Chip Dilution from Multiple Concentrations of a Sample Fluid Using Digital Microfluidics.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013
Proceedings of the 2013 IEEE International Test Conference, 2013
Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs.
Proceedings of the 2013 IEEE International Test Conference, 2013
A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs.
Proceedings of the 2013 IEEE International Test Conference, 2013
Routing-aware resource allocation for mixture preparation in digital microfluidic biochips.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
On Producing Linear Dilution Gradient of a Sample with a Digital Microfluidic Biochip.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Proceedings of the 2013 International Symposium on Electronic System Design, 2013
Optimization of polymerase chain reaction on a cyberphysical digital microfluidic biochip.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis.
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Design of cyberphysical digital microfluidic biochips under completion-time uncertainties in fluidic operations.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 22nd Asian Test Symposium, 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
Optimization Techniques for the Synchronization of Concurrent Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Integrated Test-Architecture Optimization and Thermal-Aware Test Scheduling for 3-D SoCs Under Pre-Bond Test-Pin-Count Constraint.
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Simultaneous Optimization of Droplet Routing and Control-Pin Mapping to Electrodes in Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage Scaling and Multiple Voltage Islands.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical Samples Using Digital Microfluidics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster-Shafer Theory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
ACM J. Emerg. Technol. Comput. Syst., 2012
J. Electron. Test., 2012
J. Electron. Test., 2012
IEEE Des. Test Comput., 2012
IEEE Des. Test Comput., 2012
Looking ahead at the role of electronic design automation in synthetic biology [From the EIC].
IEEE Des. Test Comput., 2012
IEEE Des. Test Comput., 2012
Proceedings of the 30th IEEE VLSI Test Symposium, 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the 2012 IEEE International Test Conference, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Diagnostic system based on support-vector machines for board-level functional diagnosis.
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
A cyberphysical synthesis approach for error recovery in digital microfluidic biochips.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 2012 IEEE International Conference on Automation Science and Engineering, 2012
Board-Level Functional Fault Diagnosis Using Learning Based on Incremental Support-Vector Machines.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant Injection.
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
Springer, ISBN: 978-1-4614-0369-2, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
IEEE J. Sel. Areas Commun., 2011
Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips.
IET Comput. Digit. Tech., 2011
J. Electron. Test., 2011
Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques.
J. Electron. Test., 2011
IEEE Des. Test Comput., 2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
Design and optimization methods for digital microfluidic biochips: A vision for functional diversity and more than moore.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks.
Proceedings of the 2011 IEEE International Test Conference, 2011
Proceedings of the 2011 IEEE International Test Conference, 2011
Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochips.
Proceedings of the 2011 International Symposium on Physical Design, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the 16th European Test Symposium, 2011
Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures.
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Digital microfluidic biochips: functional diversity, more than moore, and cyberphysical systems.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Test Scheduling for Multicore SoCs with Dynamic Voltage Scaling and Multiple Voltage Islands.
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Deterministic test for the reproduction and detection of board-level functional failures.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
Test Infrastructure Design - for Digital, Mixed-Signal and Hierarchical SOCs.
LAP Lambert Academic Publishing, ISBN: 978-3-8433-7359-3, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Optimization of Dilution and Mixing of Biochemical Samples Using Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Gate-Sizing-Based Single V<sub>dd</sub> Test for Bridge Defects in Multivoltage Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Design Tools for Digital Microfluidic Biochips: Toward Functional Diversification and More Than Moore.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Digital Microfluidic Logic Gates and Their Application to Built-in Self-Test of Lab-on-Chip.
IEEE Trans. Biomed. Circuits Syst., 2010
Microelectron. J., 2010
Integrated control-path design and error recovery in the synthesis of digital microfluidic lab-on-chip.
ACM J. Emerg. Technol. Comput. Syst., 2010
Int. J. Distributed Sens. Networks, 2010
An Energy-Efficient Data Delivery Scheme for Delay-Sensitive Traffic in Wireless Sensor Networks.
Int. J. Distributed Sens. Networks, 2010
J. Electron. Test., 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Synchronization of Concurrently-Implemented Fluidic Operations in Pin-Constrained Digital Microfluidic Biochips.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage.
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
Digital microfluidic biochips: A vision for functional diversity and more than moore.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 15th European Test Symposium, 2010
Soft error-aware design optimization of low power and time-constrained embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2010
High-quality pattern selection for screening small-delay defects considering process variations and crosstalk.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System Test.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Proceedings of the 19th IEEE Asian Test Symposium, 2010
Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional Failures.
Proceedings of the 19th IEEE Asian Test Symposium, 2010
CRC Press, ISBN: 978-1-4398-1915-9, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.
ACM Trans. Design Autom. Electr. Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.
IEEE Trans. Computers, 2009
IEEE Trans. Biomed. Circuits Syst., 2009
Guest Editorial - Selected Papers from the IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW), 2008.
IEEE Trans. Biomed. Circuits Syst., 2009
ACM J. Emerg. Technol. Comput. Syst., 2009
Int. J. Parallel Program., 2009
IET Comput. Digit. Tech., 2009
Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics.
IET Comput. Digit. Tech., 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
ACM Trans. Design Autom. Electr. Syst., 2008
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
ACM Trans. Design Autom. Electr. Syst., 2008
A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
IEEE Trans. Biomed. Circuits Syst., 2008
Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips.
ACM J. Emerg. Technol. Comput. Syst., 2008
ACM J. Emerg. Technol. Comput. Syst., 2008
Thermal-Aware Test Access Mechanism and Wrapper Design Optimization for System-on-Chips.
IEICE Trans. Inf. Syst., 2008
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.
J. Electron. Test., 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
Proceedings of the Nano-Net - Third International ICST Conference, 2008
Built-in Self-Test and Fault Diagnosis for Lab-on-Chip Using Digital Microfluidic Logic Gates.
Proceedings of the 2008 IEEE International Test Conference, 2008
Interconnect-Aware and Layout-Oriented Test-Pattern Selection for Small-Delay Defects.
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 2008 International Symposium on Physical Design, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Design and optimization of a digital microfluidic biochip for protein crystallization.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips.
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Mob. Comput., 2007
Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE Trans. Computers, 2007
Parallel Scan-Like Test and Multiple-Defect Diagnosis for Digital Microfluidic Biochips.
IEEE Trans. Biomed. Circuits Syst., 2007
Automated design of pin-constrained digital microfluidic biochips under droplet-interference constraints.
ACM J. Emerg. Technol. Comput. Syst., 2007
Redundancy Analysis and a Distributed Self-Organization Protocol for Fault-Tolerant Wireless Sensor Networks.
Int. J. Distributed Sens. Networks, 2007
J. Electron. Test., 2007
J. Electron. Test., 2007
IEEE Des. Test Comput., 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Proceedings of the 4th Annual International Conference on Mobile and Ubiquitous Systems (MobiQuitous 2007), 2007
Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs.
Proceedings of the 2007 IEEE International Test Conference, 2007
Proceedings of the 2007 IEEE International Test Conference, 2007
Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips.
Proceedings of the 12th European Test Symposium, 2007
A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression.
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects.
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 16th Asian Test Symposium, 2007
Scan Testing for Complete Coverage of Path Delay Faults with Reduced Test Data Volume, Test Application Time, and Hardware Cost.
Proceedings of the 16th Asian Test Symposium, 2007
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
CRC Press, ISBN: 978-0-8493-9009-8, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
ACM Trans. Design Autom. Electr. Syst., 2006
ACM Trans. Design Autom. Electr. Syst., 2006
A unified approach for fault tolerance and dynamic power management in fixed-priority real-time embedded systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Microfluidics-Based Biochips: Technology Issues, Implementation Platforms, and Design-Automation Challenges.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Defect Tolerance Based on Graceful Degradation and Dynamic Reconfiguration for Digital Microfluidics-Based Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy.
ACM J. Emerg. Technol. Comput. Syst., 2006
J. Electron. Test., 2006
Proceedings of the IEEE Wireless Communications and Networking Conference, 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs.
Proceedings of the 2006 IEEE International Test Conference, 2006
Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006
An evaluation of the impact of gate oxide tunneling on dual-<i>V<sub>t</sub></i>-based leakage reduction techniques.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Reconfiguration-Based Defect Tolerance for Microfluidic Biochips.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
Test set enrichment using a probabilistic fault model and the theory of output deviations.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*.
Proceedings of the 43rd Design Automation Conference, 2006
Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
An Efficient Test Pattern Selection Method for Improving Defect Coverage with Reduced Test Data Volume and Test Application Time.
Proceedings of the 15th Asian Test Symposium, 2006
Compressing Test Data for Deterministic BIST Using a Reconfigurable Scan Arhcitecture.
Proceedings of the 15th Asian Test Symposium, 2006
Proceedings of the 15th Asian Test Symposium, 2006
2005
Modular Testing and Built-In Self-Test of Embedded Cores in System-on-Chip Integrated Circuits.
Proceedings of the Embedded Systems Handbook., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Computing reliability and message delay for Cooperative wireless distributed sensor networks subject to random failures.
IEEE Trans. Reliab., 2005
Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems.
ACM Trans. Embed. Comput. Syst., 2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
A Distributed Coverage- and Connectivity-Centric Technique for Selecting Active Nodes in Wireless Sensor Networks.
IEEE Trans. Computers, 2005
Location-Aided Flooding: An Energy-Efficient Data Dissemination Protocol for Wireless Sensor Networks.
IEEE Trans. Computers, 2005
ACM J. Emerg. Technol. Comput. Syst., 2005
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 10th European Test Symposium, 2005
Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the Distributed Computing in Sensor Systems, 2005
Yield Enhancement of Digital Microfluidics-Based Biochips Using Space Redundancy and Local Reconfiguration.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Multi-frequency wrapper design and optimization for embedded cores under average power constraints.
Proceedings of the 42nd Design Automation Conference, 2005
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips.
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the Handbook on Theoretical and Algorithmic Aspects of Sensor, 2005
Springer, ISBN: 978-1-85233-951-7, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Knowl. Data Eng., 2004
ACM Trans. Embed. Comput. Syst., 2004
Dynamic adaptation for fault tolerance and power management in embedded real-time systems.
ACM Trans. Embed. Comput. Syst., 2004
Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Test set embedding for deterministic BIST using a reconfigurable interconnection network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
J. Parallel Distributed Comput., 2004
On Using Exponential-Golomb Codes and Subexponential Codes for System-on-a-Chip Test Data Compression.
J. Electron. Test., 2004
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST.
J. Electron. Test., 2004
Analysis of Test Application Time for Test Data Compression Methods Based on Compression Codes.
J. Electron. Test., 2004
Concurrent Testing of Droplet-Based Microfluidic Systems for Multiplexed Biomedical Assays.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems.
Proceedings of the 2004 Design, 2004
Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Energy-aware deterministic fault tolerance in distributed real-time embedded systems.
Proceedings of the 41th Design Automation Conference, 2004
Techniques to Reduce Communication and Computation Energy in Wireless Sensor Networks.
Proceedings of the Handbook of Sensor Networks, 2004
2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Test data compression using dictionaries with selective entries and fixed-length indices.
ACM Trans. Design Autom. Electr. Syst., 2003
Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets.
IEEE Trans. Instrum. Meas., 2003
Space compaction of test responses using orthogonal transmission functions [logic testing].
IEEE Trans. Instrum. Meas., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.
IEEE Trans. Computers, 2003
Test Data Compression and Test Resource Partitioning for System-on-a-Chip Using Frequency-Directed Run-Length (FDR) Codes.
IEEE Trans. Computers, 2003
Ad Hoc Networks, 2003
Sensor placement for effective coverage and surveillance in distributed sensor networks.
Proceedings of the 2003 IEEE Wireless Communications and Networking, 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003
Proceedings of the First IEEE International Conference on Pervasive Computing and Communications (PerCom'03), 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Proceedings of the Proceedings IEEE INFOCOM 2003, The 22nd Annual Joint Conference of the IEEE Computer and Communications Societies, San Franciso, CA, USA, March 30, 2003
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Generalized Network Flow Techniques for Dynamic Voltage Scaling in Hard Real-Time Systems.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Proceedings of the Global Telecommunications Conference, 2003
Proceedings of the 8th European Test Workshop, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the Embedded Software for SoC, 2003
2002
Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering.
IEEE Trans. Instrum. Meas., 2002
Design of reconfigurable composite microsystems based on hardware/software codesign principles.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
Test data compression and decompression based on internal scanchains and Golomb coding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEEE Trans. Computers, 2002
High Performance Sensor Integration in Distributed Sensor Networks Using Mobile Agents.
Int. J. High Perform. Comput. Appl., 2002
J. Electron. Test., 2002
How Useful are the ITC 02 SoC Test Benchmarks?
IEEE Des. Test Comput., 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the 8th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2002), 2002
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
An Interval-Based Diagnosis Scheme for Identifying Failing Vectors in a Scan-BIST Environment.
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression.
Proceedings of the 2002 Design, 2002
Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.
Proceedings of the 39th Design Automation Conference, 2002
Reduction of SOC test data volume, scan power and testing time using alternating run-length codes.
Proceedings of the 39th Design Automation Conference, 2002
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
Frontiers in electronic testing 20, Kluwer / Springer, ISBN: 978-1-4020-7119-5, 2002
2001
VLSI Design, 2001
IEEE Trans. Syst. Man Cybern. Part C, 2001
ACM Trans. Design Autom. Electr. Syst., 2001
Scheduling of microfluidic operations for reconfigurabletwo-dimensional electrowetting arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
System-on-a-chip test-data compression and decompressionarchitectures based on Golomb codes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
J. Electron. Test., 2001
Design of Parameterizable Error-Propagating Space Compactors for Response Observation.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Frequency-Directed Run-Length (FDR) Codes with Application to System-on-a-Chip Test Data Compression.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 2001 International Symposium on Information Technology (ITCC 2001), 2001
Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 38th Design Automation Conference, 2001
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
A deterministic scan-BIST architecture with application to field testing of high-availability systems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems.
Proceedings of ASP-DAC 2001, 2001
Proceedings of ASP-DAC 2001, 2001
2000
Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters.
IEEE Trans. Very Large Scale Integr. Syst., 2000
IEEE Trans. Instrum. Meas., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Space Compaction of Test Responses for IP Cores Using Orthogonal Transmission Functions.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Design of System-on-a-Chip Test Access Architectures using Integer Linear Programming.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Design of system-on-a-chip test access architectures under place-and-route and power constraints.
Proceedings of the 37th Conference on Design Automation, 2000
1999
Inf. Process. Lett., 1999
J. Electron. Test., 1999
Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
IEEE Trans. Inf. Theory, 1998
IEEE Trans. Instrum. Meas., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998
IEEE Trans. Computers, 1998
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998
1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Inf. Process. Lett., 1997
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
J. Electron. Test., 1996
1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
Proceedings of the Proceedings IEEE International Test Conference 1995, 1995
1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1993
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993
Proceedings of the Digest of Papers: FTCS-23, 1993