Krishna Chakravadhanula

According to our database, Krishna Chakravadhanula authored at least 16 papers between 2007 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

PPA Optimization of Test Points in Automotive Designs.

Brian Foutz, Sarthak Singhal, Prateek Kumar Rai, Krishna Chakravadhanula, Vivek Chickermane, Bharath Nandakumar, Sameer Chillarige, Christos Papameletis, Satish Ravichandran

Proceedings of the IEEE International Test Conference, 2022

2019

Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications.

Christos Papameletis, Vivek Chickermane, Brian Foutz, Sarthak Singhal, Krishna Chakravadhanula

Proceedings of the IEEE International Test Conference, 2019

2018

Improving Diagnosis Resolution and Performance at High Compression Ratios.

Sameer Chillarige, Atul Chhabra, Anil Malik, Bharath Nandakumar, Joe Swenton, Krishna Chakravadhanula

Proceedings of the IEEE International Test Conference, 2018

2017

High throughput multiple device diagnosis system.

Sameer Chillarige, Anil Malik, Sharjinder Singh, Joe Swenton, Krishna Chakravadhanula

Proceedings of the IEEE International Test Conference, 2017

Advancing test compression to the physical dimension.

Krishna Chakravadhanula, Vivek Chickermane, Paul Cunningham, Brian Foutz, Dale Meehl, Louis Milano, Christos Papameletis, David Scott, Steev Wilcox

Proceedings of the IEEE International Test Conference, 2017

2015

A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures.

Sameer Chillarige, S. Virdi, Anil Malik, Krishna Chakravadhanula, Vivek Chickermane, Joe Swenton, G. Vandling

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

2014

Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices.

Srivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Efficient testing of hierarchical core-based SOCs.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen

Proceedings of the 2014 International Test Conference, 2014

2013

SmartScan - Hierarchical test compression for pin-limited low power designs.

Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj

Proceedings of the 2013 IEEE International Test Conference, 2013

2010

Low cost at-speed testing using On-Product Clock Generation compatible with test compression.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Automating IEEE 1500 Core Test—An EDA Perspective.

Krishna Chakravadhanula, Vivek Chickermane

IEEE Des. Test Comput., 2009

Capture power reduction using clock gating aware test generation.

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang

Proceedings of the 2009 IEEE International Test Conference, 2009

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?.

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs.

Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula

Proceedings of the 2008 IEEE International Test Conference, 2008

Test Generation for State Retention Logic.

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Low Power Reduced Pin Count Test Methodology.

Krishna Chakravadhanula, Nitin Parimi, Brian Foutz, Bing Li, Vivek Chickermane

Proceedings of the 16th Asian Test Symposium, 2007