Kozo Kinoshita

According to our database, Kozo Kinoshita authored at least 116 papers between 1970 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

SAT-Based Test Generation for Open Faults Using Fault Excitation Caused by Effect of Adjacent Lines.

Jun Yamashita, Hiroyuki Yotsuyanagi, Masaki Hashizume, Kozo Kinoshita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2010

Current-based testable design of level shifters in liquid crystal display drivers.

Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita

Proceedings of the 15th European Test Symposium, 2010

2008

Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.

Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

J. Electron. Test., 2008

2007

A statistical error model for image sensors and its testing.

Hideyuki Ichihara, Toshimasa Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita

Syst. Comput. Jpn., 2007

A Novel ATPG Method for Capture Power Reduction during Scan Testing.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2007

2006

A New Method for Low-Capture-Power Test Generation for Scan Testing.

Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2006

A Per-Test Fault Diagnosis Method Based on the <i>X</i>-Fault Model.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2006

A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2005

Fault Diagnosis of Physical Defects Using Unknown Behavior Model.

Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita

J. Comput. Sci. Technol., 2005

On Design for I_DDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.

Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2005

Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.

Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita

J. Electron. Test., 2005

On Low-Capture-Power Test Generation for Scan Testing.

Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Low-capture-power test generation for scan-based at-speed testing.

Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004

On per-test fault diagnosis using the X-fault model.

Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.

Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2003

Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs.

Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Reducing Scan Shifts Using Folding Scan Trees.

Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

Fault Diagnosis for Physical Defects of Unknown Behaviors.

Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

A BIST Circuit for IDDQ Tests.

Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Built-in Self-Test for crosstalk faults in a digital VLSI.

Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita

Syst. Comput. Jpn., 2002

Foreword.

Kozo Kinoshita

J. Electron. Test., 2002

On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.

Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits.

Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita

Proceedings of the 1st IEEE International Workshop on Electronic Design, 2002

Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits.

Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

IDDQ Sensing Technique for High Speed IDDQ Testing.

Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits.

Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Static test compaction for IDDQ testing of bridging faults in sequential circuits.

Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita

Syst. Comput. Jpn., 2000

Compaction of IDDQ Test Sequence Using Reassignment Method.

Toshiyuki Maeda, Kozo Kinoshita

J. Electron. Test., 2000

Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.

Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita

J. Electron. Test., 2000

Test Transformation to Improve Compaction by Statistical Encoding.

Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Precise test generation for resistive bridging faults of CMOS combinational circuits.

Toshiyuki Maeda, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Memory reduction of I_DDQ test compaction for internal and external bridging faults.

Toshiyuki Maeda, Kozo Kinoshita

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.

Arabi Keshk, Yukiya Miura, Kozo Kinoshita

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Test sequence compaction for sequential circuits with reset states.

Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A high-speed IDDQ sensor implementation.

Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Fault models and test generation for IDDQ testing: embedded tutorial.

Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita

Proceedings of ASP-DAC 2000, 2000

1999

Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits.

Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

On Test Generation with A Limited Number of Tests.

Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

IDDQ Current Dependency on Test Vectors and Bridging Resistance.

Arabi Keshk, Kozo Kinoshita, Yukiya Miura

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits.

Arabi Keshk, Kozo Kinoshita, Yukiya Miura

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.

Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.

Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Undetectable Fault Removal of Sequential Circuits Based on Unreachable States.

Hiroyuki Yotsuyanagi, Kozo Kinoshita

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Design for Diagnosability of CMOS Circuits.

Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA.

Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification.

Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.

Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

A High-Speed IDDQ Sensor for Low-Voltage ICs.

Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

A diagnosis method for single logic design errors in gate-level combinational circuits.

Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita

Syst. Comput. Jpn., 1997

I_DDQ test vector selection for transistor short fault testing.

Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita

Syst. Comput. Jpn., 1997

On invariant implication relations for removing partial circuits.

Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara

Syst. Comput. Jpn., 1997

Synthesis of Sequential Circuits by Redundancy Removal and Retiming.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

J. Electron. Test., 1997

A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.

Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Design of partially parallel scan chain.

Yoshinobu Higami, Kozo Kinoshita

Proceedings of the European Design and Test Conference, 1997

An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits.

Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

On Acceleration of Logic Circuits Optimization Using Implication Relations.

Hideyuki Ichihara, Kozo Kinoshita

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits.

Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita

Proceedings of the Digest of Papers: FTCS-26, 1996

Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.

Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Evaluation of the maximum number of switching gates for CMOS circuits.

Hiroaki Ueda, Kozo Kinoshita

Syst. Comput. Jpn., 1995

Test pattern generation for crosstalk faults considering the gate delay.

Noriyoshi Itazaki, Kozo Kinoshita, Hisao Naitoh

Syst. Comput. Jpn., 1995

Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

IEICE Trans. Inf. Syst., 1995

Testing of <i>k</i>-FR Circuits under Highly Observable Condition.

Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita

IEICE Trans. Inf. Syst., 1995

Efficient Guided-Probe Fault Location Method for Sequential Circuits.

Xiaoqing Wen, Kozo Kinoshita, Hideo Tamamoto, Hiroshi Yokoyama

IEICE Trans. Inf. Syst., 1995

Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis.

Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita

IEICE Trans. Inf. Syst., 1995

Partial scan design and test sequence generation based on reduced scan shift method.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

J. Electron. Test., 1995

Resynthesis for sequential circuits designed with a specified initial state.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

Synthesis for Testability by Sequential Redundancy Removal Using Retiming.

Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita

Proceedings of the Digest of Papers: FTCS-25, 1995

Transistor leakage fault location with ZDDQ measurement.

Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Low power design and its testability.

Hiroaki Ueda, Kozo Kinoshita

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Test sequence compaction by reduced scan shift and retiming.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

An approach to the analysis and detection of crosstalk faults in digital VLSI circuits.

Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

On compacting test sets by addition and removal of test vectors.

Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

Reduced Scan Shift: A New Testing Method for Sequential Circuit.

Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit.

Yukiya Miura, Sachio Naito, Kozo Kinoshita

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Design of testing circuit and test generation for built-in current testing.

Yukiya Miura, Yasushi Wada, Kozo Kinoshita

Syst. Comput. Jpn., 1993

Removal of redundancy in combinational circuits under classification of undetectable faults.

Seiji Kajihara, Kozo Kinoshita, Haruko Shiba

Syst. Comput. Jpn., 1993

Test generation for multiple faults based on parallel vector pair analysis.

Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

A Testable Design of Logic Circuits under Highly Observable Condition.

Xiaoqing Wen, Kozo Kinoshita

IEEE Trans. Computers, 1992

Testable Designs of Sequential Circuits Under Highly Observable Condition.

Xiaoqing Wen, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Circuit Design for Built-in Current Testing.

Yukiya Miura, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults.

Seiji Kajihara, Haruko Shiba, Kozo Kinoshita

Proceedings of the Digest of Papers: FTCS-22, 1992

1991

Stuck-open faults test generation for cmos combinational circuits.

Seiji Kajihara, Noriyoshi Itazaki, Kozo Kinoshita

Syst. Comput. Jpn., 1991

An approach to the analysis and test of crosstalk faults in digital VLSI circuits.

Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita

Proceedings of the conference on European design automation, 1991

1990

A built-in self-test algorithm for row/column pattern sensitive faults in RAMs.

Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita

IEEE J. Solid State Circuits, April, 1990

Extended selection of switching target faults in CONT algorithm for test generation.

Yuzo Takamatsu, Kozo Kinoshita

J. Electron. Test., 1990

On the evaluation of process-fault tolerance ability of CMOS integrated circuits.

Etienne Sicard, Kozo Kinoshita

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Fault detection and diagnosis of k-UCP circuits under totally observable condition.

Xiaoqing Wen, Kozo Kinoshita

Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

1989

CONT: a concurrent test generation system.

Yuzo Takamatsu, Kozo Kinoshita

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Test pattern generation for circuits with tri-state modules by Z-algorithm.

Noriyoshi Itazaki, Kozo Kinoshita

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability.

Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the Proceedings International Test Conference 1989, 1989

Row/column pattern sensitive fault detection in RAMs via built-in self-test.

Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1987

Built-In Self-Testing RAM: A Practical Alternative.

Kewal K. Saluja, Siew H. Sng, Kozo Kinoshita

IEEE Des. Test, 1987

1986

Built-In Testing of Memory Using an On-Chip Compact Testing Scheme.

Kozo Kinoshita, Kewal K. Saluja

IEEE Trans. Computers, 1986

Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm.

Noriyoshi Itazaki, Kozo Kinoshita

Proceedings of the Proceedings International Test Conference 1986, 1986

1985

Test Pattern Generation for API Faults in RAM.

Kewal K. Saluja, Kozo Kinoshita

IEEE Trans. Computers, 1985

Design of Programmable Logic Arrays for Parallel Testing.

C. Boswell, Kewal K. Saluja, Kozo Kinoshita

Comput. Syst. Sci. Eng., 1985

A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead.

Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita

Proceedings of the Proceedings International Test Conference 1985, 1985

1984

Built-in Testing of Memory Using On-chip Compact Testing Scheme.

Kozo Kinoshita, Kewal K. Saluja

Proceedings of the Proceedings International Test Conference 1984, 1984

1983

An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.

Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara

IEEE Trans. Computers, 1983

Design of High-Level Test Language for Digital LSI.

Takuji Okamoto, Hiroyuki Shibata, Kozo Kinoshita

Proceedings of the Proceedings International Test Conference 1983, 1983

Test generation for scan design circuits with tri-state modules and bidirectional terminals.

Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara

Proceedings of the 20th Design Automation Conference, 1983

1981

A Design of Programmable Logic Arrays with Universal Tests.

Hideo Fujiwara, Kozo Kinoshita

IEEE Trans. Computers, 1981

An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2.

Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita

Proceedings of the 18th Design Automation Conference, 1981

1979

On the Number of Fanout-Free Functions and Unate Cascade Functions.

Tsutomu Sasao, Kozo Kinoshita

IEEE Trans. Computers, 1979

Conservative Logic Elements and Their Universality.

Tsutomu Sasao, Kozo Kinoshita

IEEE Trans. Computers, 1979

1978

Cascade Realization of 3-Input 3-Output Conservative Logic Circuits.

Tsutomu Sasao, Kozo Kinoshita

IEEE Trans. Computers, 1978

Realization of Minimum Circuits with Two-Input Conservative Logic Elements.

Tsutomu Sasao, Kozo Kinoshita

IEEE Trans. Computers, 1978

Some Existence Theorems for Probabilistically Diagnosable Systems.

Hideo Fujiwara, Kozo Kinoshita

IEEE Trans. Computers, 1978

Connection Assignments for Probabilistically Diagnosable Systems.

Hideo Fujiwara, Kozo Kinoshita

IEEE Trans. Computers, 1978

On the Computational Complexity of System Diagnosis.

Hideo Fujiwara, Kozo Kinoshita

IEEE Trans. Computers, 1978

LORES - Logic Reorganization System.

Shunichiro Nakamura, Shinichi Murai, Chiyoji Tanaka, Masayuki Terai, Hideo Fujiwara, Kozo Kinoshita

Proceedings of the 15th Design Automation Conference, 1978

1976

On Magnetic Bubble Logic Circuits.

Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda

IEEE Trans. Computers, 1976

1975

Easily Testable Sequential Machines with Extra Inputs.

Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita

IEEE Trans. Computers, 1975

1974

Design of Diagnosable Sequential Machines Utilizing Extra Outputs.

Hideo Fujiwara, Kozo Kinoshita

IEEE Trans. Computers, 1974

1970

Sequential Machines Capable of Fault Diagnosis.

Shin-ichi Murakami, Kozo Kinoshita, Hiroshi Ozaki

IEEE Trans. Computers, 1970