Koyo Nitta

According to our database, Koyo Nitta authored at least 26 papers between 1999 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

An Efficient Reference Image Sharing Method for the Image-Division Parallel Video Encoding Architecture.

Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi

IEICE Trans. Electron., June, 2023

High-definition technology of AI inference scheme for object detection on edge/terminal.

Hiroyuki Uzawa, Shuhei Yoshida, Yukou Iinuma, Saki Hatta, Daisuke Kobayashi, Yuya Omori, Yusuke Horishita, Ken Nakamura, Shuichi Takada, Hassan Toorabally, Koyo Nitta, Koji Yamazaki, Kimikazu Sano

IEICE Electron. Express, 2023

2022

OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization.

Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture.

Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato, Hiroe Iwasaki, Hiroaki Kobayashi

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022

2021

FPGA-based network microburst analysis system with efficient packet capturing.

Shuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda, Koyo Nitta

JOCN, 2021

A Power Reduction Scheme with Partial Sleep Control of ONU Frame Buffer in Operation.

Hiroyuki Uzawa, Kazuhiko Terada, Koyo Nitta

IEICE Trans. Commun., 2021

Programmable Hardware Accelerator for Finite-State-Machine Processing in Flexible Access Network Systems.

Saki Hatta, Nobuyuki Tanaka, Hiroyuki Uzawa, Koyo Nitta

IEICE Trans. Commun., 2021

2020

Real-Time Image Processing Based on Service Function Chaining Using CPU-FPGA Architecture.

Yuta Ukon, Koji Yamazaki, Koyo Nitta

IEICE Trans. Commun., 2020

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.

Ken Nakamura, Daisuke Kobayashi, Yuya Omori, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki

IEICE Trans. Electron., 2020

FPGA-Based Network Microburst Analysis System with Flow Specification and Efficient Packet Capturing.

Shuhei Yoshida, Yuta Ukon, Shoko Ohteru, Hiroyuki Uzawa, Namiko Ikeda, Koyo Nitta

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.

Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018

A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K.

Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu

IEEE Trans. Very Large Scale Integr. Syst., 2018

Video Service Function Chaining with a Real-time Packet Reordering Circuit.

Yuta Ukon, Koji Yamazaki, Koyo Nitta

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Flow Cache Cleansing with FPGA Hash Pipe for Highly Stabilized Software Data Plane.

Koji Yamazaki, Yuta Ukon, Shuhei Yoshida, Saki Hatta, Yusuke Sekihara, Shoko Ohteru, Tomoaki Kawamura, Takahiro Hatano, Koyo Nitta, Akihiko Miyazaki

Proceedings of the IEEE 19th International Conference on High Performance Switching and Routing, 2018

2015

Motion Estimation and Compensation Hardware Architecture with Hierarchy of Flexibility in Video Encoder LSIs.

Koyo Nitta

PhD thesis, 2015

Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability.

Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu

Proceedings of the Symposium on VLSI Circuits, 2015

Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure.

Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2013

Residue role assignment based transform partition predetermination on HEVC.

Jia Su, Koyo Nitta, Mitsuo Ikeda, Atsushi Shimizu

Proceedings of the IEEE International Conference on Image Processing, 2013

2012

An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures.

Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma

IEICE Trans. Electron., 2012

MVC real-time video encoder for full-HDTV 3D video.

Mitsuo Ikeda, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Hiroe Iwasaki, Yasuyuki Nakajima, Koyo Nitta, Yasuko Takahashi, Kazuya Yokohari, Daisuke Kobayashi, Kazuto Kamikura, Hirohisa Jozawa

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

2008

Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI.

Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.

Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima

IEEE Trans. Very Large Scale Integr. Syst., 2007

2003

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.

Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo

Proceedings of the 2003 Design, 2003

1999

A 4: 2: 2P@ML MPEG-2 video encoder board using an enhanced MP@ML video encoder LSI.

Takeshi Yoshitome, Toshihiro Minami, Mitsuo Ikeda, Koyo Nitta, Kazuhito Suguri

IEEE Trans. Consumer Electron., 1999

SuperENC: MPEG-2 video encoder chip.

Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai

IEEE Micro, 1999

An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture.

Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura

Proceedings of the 1999 Design, 1999