Koushik K. Das

According to our database, Koushik K. Das authored at least 11 papers between 2003 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2016

Security, Compliance, and Agile Deployment of Personal Identifiable Information Solutions on a Public Cloud.

Yasuharu Katsuno, Ashish Kundu, Koushik K. Das, Hitomi Takahashi, Robert Schloss, Prasenjit Dey, Mukesh K. Mohania

Proceedings of the 9th IEEE International Conference on Cloud Computing, 2016

2009

Yield estimation of SRAM circuits using "Virtual SRAM Fab".

Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Reducing parasitic BJT effects in partially depleted SOI digital logic circuits.

Koushik K. Das, Ching-Te Chuang, Richard B. Brown

Microelectron. J., 2008

2007

An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability.

Koushik K. Das, Steven G. Walker, Manjul Bhushan

Proc. IEEE, 2007

2006

Ultralow-voltage, minimum-energy CMOS.

Scott Hanson, Bo Zhai, Kerry Bernstein, David T. Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester

IBM J. Res. Dev., 2006

High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.

Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2004

Nanoscale CMOS circuit leakage power reduction by double-gate device.

Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003

Ultra Low-Leakage Power Strategies for Sub-1 V VLSI: Novel Circuit Styles and Design Methodologies for Partially Depleted Silicon-On-Insulator (PD-SOI) CMOS Technology.

Koushik K. Das, Richard B. Brown

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS.

Koushik K. Das, Richard B. Brown

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology.

Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology.

Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown

Proceedings of the ESSCIRC 2003, 2003