Kouichi Kanda

According to our database, Kouichi Kanda authored at least 23 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Digital Annealing Engine for High-speed Solving of Constrained Binary Quadratic Problems on Multiple GPUs.

Kentaro Katayama, Noboru Yoneoka, Kouichi Kanda, Hirotaka Tamura, Hiroshi Nakayama, Yasuhiro Watanabe

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

2022

MAQO: A Scalable Many-Core Annealer for Quadratic Optimization.

Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

MAQO: A Scalable Many-Core Annealer for Quadratic Optimization on a Stratix 10 FPGA.

Mohammad Bagherbeik, Wentao Xu, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

2020

A Permutational Boltzmann Machine with Parallel Tempering for Solving Combinatorial Optimization Problems.

Mohammad Bagherbeik, Parastoo Ashtari, Seyed Farzad Mousavi, Kouichi Kanda, Hirotaka Tamura, Ali Sheikholeslami

Proceedings of the Parallel Problem Solving from Nature - PPSN XVI, 2020

2015

A 0.33 nJ/bit IEEE802.15.6/Proprietary MICS/ISM Wireless Transceiver With Scalable Data Rate for Medical Implantable Applications.

Ao Ba, Maja Vidojkovic, Kouichi Kanda, Nauman F. Kiyani, Maarten Lont, Xiongchuan Huang, Xiaoyan Wang, Cui Zhou, Yao-Hong Liu, Ming Ding, Benjamin Busze, Shoichi Masui, Makoto Hamaminato, Hiroyuki Sato, Kathleen Philips, Harmke de Groot

IEEE J. Biomed. Health Informatics, 2015

A 3.5mW 315/400MHz IEEE802.15.6/proprietary mode digitally-tunable radio SoC with integrated digital baseband and MAC processor in 40nm CMOS.

Christian Bachmann, Maja Vidojkovic, Xiongchuan Huang, Maarten Lont, Yao-Hong Liu, Ming Ding, Benjamin Busze, Jordy Gloudemans, Hans Giesen, Adnane Sbai, Gert-Jan van Schaik, Nauman F. Kiyani, Kouichi Kanda, Kazuaki Oishi, Shoichi Masui, Kathleen Philips, Harmke de Groot

Proceedings of the Symposium on VLSI Circuits, 2015

2014

Radio channel characterization for 400 MHz implanted devices.

Hans W. Pflug, Hubregt J. Visser, Nauman F. Kiyani, Guido Dolmans, Kathleen Philips, Kouichi Kanda, Makoto Hamaminato, Shoichi Masui

Proceedings of the IEEE Wireless Communications and Networking Conference, 2014

9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications.

Maja Vidojkovic, Xiongchuan Huang, Xiaoyan Wang, Cui Zhou, Ao Ba, Maarten Lont, Yao-Hong Liu, Pieter Harpe, Ming Ding, Ben Busze, Nauman F. Kiyani, Kouichi Kanda, Shoichi Masui, Kathleen Philips, Harmke de Groot

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

A fully integrated triple-band CMOS power amplifier for WCDMA mobile handsets.

Kouichi Kanda, Yoichi Kawano, Takao Sasaki, Noriaki Shirai, Tetsuro Tamura, Shigeaki Kawai, Masahiro Kudo, Tomotoshi Murakami, Hiroyuki Nakamoto, Nobumasa Hasegawa, Hideki Kano, Nobuhiro Shimazui, Akiko Mineyama, Kazuaki Oishi, Masashi Shima, Naoyoshi Tamura, Toshihide Suzuki, Toshihiko Mori, Kimitoshi Niratsuka, Shinji Yamaura

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011

A 60-GHz Injection-Locked Frequency Divider Using Multi-Order <i>LC</i> Oscillator Topology for Wide Locking Range.

Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda

IEICE Trans. Electron., 2011

2010

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS.

Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2010

A 60-GHz 1.65mW 25.9% locking range multi-order LC oscillator based injection locked frequency divider in 65nm CMOS.

Keita Takatsu, Hirotaka Tamura, Takuji Yamamoto, Yoshiyasu Doi, Kouichi Kanda, Takayuki Shibasaki, Tadahiro Kuroda

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS.

Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

IEEE J. Solid State Circuits, 2009

A single-40Gb/s dual-20Gb/s serializer IC with SFI-5.2 interface in 65nm CMOS.

Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range.

Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2008

2007

18-GHz Clock Distribution Using a Coupled VCO Array.

Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

IEICE Trans. Electron., 2007

A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.

Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

Managing subthreshold leakage in charge-based analog circuits with low-V_TH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS).

Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai

IEEE J. Solid State Circuits, 2006

Circuits for CMOS High-Speed I/O in Sub-100 nm Technologies.

Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Kouichi Kanda, Kohtaroh Gotoh, Hideki Ishida, Junji Ogawa

IEICE Trans. Electron., 2006

2005

Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-<i>V_DD</i> SRAM's.

Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai

IEICE Trans. Electron., 2005

Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS).

Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi, Takayasu Sakurai

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

90% write power-saving SRAM using sense-amplifying memory cell.

Kouichi Kanda, Hattori Sadaaki, Takayasu Sakurai

IEEE J. Solid State Circuits, 2004

2001

Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs.

Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai

IEEE J. Solid State Circuits, 2001