Kotaro Shimamura

According to our database, Kotaro Shimamura authored at least 10 papers between 1994 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

FS-Boost: Communication-Efficient Federated Subtree-Based Gradient Boosting Decision Trees.

Kotaro Shimamura, Shinya Takamaeda-Yamazaki

Proceedings of the 21st IEEE Consumer Communications & Networking Conference, 2024

2023

Measurement Results of Real Circuit Delay Degradation under Realistic Workload.

Kotaro Shimamura, Takeshi Takehara, Naohiro Ikeda

IPSJ Trans. Syst. LSI Des. Methodol., 2023

2020

Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs.

Yusuke Kanno, Tadanobu Toba, Kotaro Shimamura, Nobuyasu Kanekawa

IEEE Trans. Very Large Scale Integr. Syst., 2020

Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator.

Kotaro Shimamura, Naohiro Ikeda

IPSJ Trans. Syst. LSI Des. Methodol., 2020

2012

DART: Dependable VLSI test architecture and its implementation.

Yasuo Sato, Seiji Kajihara, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue, Yukiya Miura, Satosni Untake, Takumi Hasegawa, Motoyuki Sato, Kotaro Shimamura

Proceedings of the 2012 IEEE International Test Conference, 2012

2006

A Single-Chip Fail-Safe Microprocessor with Memory Data Comparison Feature.

Kotaro Shimamura, Takeshi Takehara, Yosuke Shima, Kunihiko Tsunedomi

Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006

1998

A Triple Redundant Controller which Adopts the Time-Sharing Fault Recovery Method and its Application to a Power Converter Controller.

Kotaro Shimamura, Yuichiro Morita, Yoshitaka Takahashi, Takashi Hotta, Shigeta Ueda, Mikiya Nohara, Mitsuyasu Kido, Seji Tanaka, Kazuhiro Imaie, Koji Sakamoto, Tatsuhito Nakajima

Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium, 1998

1996

2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor.

Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada, Takahiro Nishiyama, Kotaro Shimamura, Shigeya Tanaka, Takashi Hotta, Teruhisa Shimizu, Hideo Sawamoto

IEEE J. Solid State Circuits, 1996

1995

A superscalar RISC processor with pseudo vector processing feature.

Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

A 120-MHz BiCMOS superscalar RISC processor.

Shigeya Tanaka, Takashi Hotta, Fumio Murabayashi, Hiromichi Yamada, Shoji Yoshida, Kotaro Shimamura, Koyo Katsura, Tadaaki Bandoh, Koichi Ikeda, Kenji Matsubara, Kouji Saitou, Tetsuo Nakano, Teruhisa Shimizu, Ryuichi Satomura

IEEE J. Solid State Circuits, April, 1994