Kostas Tsoumanis

According to our database1, Kostas Tsoumanis authored at least 21 papers between 2012 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Τεχνικές βελτιστοποίησης σύνθετων αριθμητικών συστημάτων
PhD thesis, 2016

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding.
IEEE Trans. Computers, 2016

Fused modulo 2n + 1 add-multiply unit for weighted operands.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015
Delta DICE: A Double Node Upset resilient latch.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Modulo 2n ± 1 Fused Add-Multiply Units.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Hybrid approximate multiplier architectures for improved power-accuracy trade-offs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A high radix montgomery multiplier with concurrent error detection.
Proceedings of the 9th International Design and Test Symposium, 2014

Modulo 2<sup>n</sup>+1 addition and multiplication for redundant operands.
Proceedings of the 9th International Design and Test Symposium, 2014

An independent dual gate SOI FinFET soft-error resilient memory cell.
Proceedings of the 9th International Design and Test Symposium, 2014

Fused modulo 2<sup>n</sup> - 1 add-multiply unit.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

On the design of efficient modulo 2<sup>n</sup>+1 multiply-add-add units.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

A segmentation-based BISR scheme.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
On the design of modulo 2<sup>n</sup>±1 residue generators.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A radiation tolerant and self-repair memory cell.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Efficient modulo 2<sup>n</sup>+1 multiplication for the idea block cipher.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012
On the Design of Configurable Modulo 2n±1 Residue Generators.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012


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