Kostas Siozios

Orcid: 0000-0002-0285-2202

Affiliations:
  • Aristotle University of Thessaloniki (AUTH), Greece


According to our database1, Kostas Siozios authored at least 144 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Online Energy Management Framework for Smart Buildings With Low-Complexity Estimators.
IEEE Embed. Syst. Lett., June, 2024

Evolutionary Approximation of Ternary Neurons for On-sensor Printed Neural Networks.
CoRR, 2024

Energy-Aware Heterogeneous Federated Learning via Approximate Systolic DNN Accelerators.
CoRR, 2024

2023
AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorch.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Thermal-Comfort Aware Online Co-Scheduling Framework for HVAC, Battery Systems, and Appliances in Smart Buildings.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., May, 2023

Hardware-Aware DNN Compression via Diverse Pruning and Mixed-Precision Quantization.
CoRR, 2023

CMOS Noise Analysis and Simulation From Low Frequency and Baseband to RF and Millimeter Wave.
IEEE Access, 2023

Enabling an Isolated and Energy-Aware Deployment of Computationally Intensive Kernels on Multi-tenant Environments.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

ICE: A Low-Cost IoT Platform Targeting Real-Time Anonymous Visitors Flow Tracking at Museums.
Proceedings of the 32nd IEEE International Symposium on Industrial Electronics, 2023

Model-Free HVAC Optimizer based on Reinforcement Learning.
Proceedings of the 32nd IEEE International Symposium on Industrial Electronics, 2023

Indoor Positioning System Evaluation in Public Rooms.
Proceedings of the 12th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2023


A Python Framework for System-on-Chip Power Integrity Simulation.
Proceedings of the IEEE International Conference on Industrial Technology, 2023

Bespoke Approximation of Multiplication-Accumulation and Activation Targeting Printed Multilayer Perceptrons.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Hardware-Aware Automated Neural Minimization for Printed Multilayer Perceptrons.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

The SERRANO platform: Stepping towards seamless application development & deployment in the heterogeneous edge-cloud continuum.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Variability-Aware Approximate Circuit Synthesis via Genetic Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Dynamic Optimization of On-Chip Memories for HLS Targeting Many-Accelerator Platforms.
IEEE Comput. Archit. Lett., 2022

Wide-Range Light Harvesting Module for Autonomous Sensor Nodes.
IEEE Access, 2022

Machine Learning based Power Converter Large Signal Simulation for Energy Harvesting Applications.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Linear and Periodic State Integrated Circuits Noise Simulation Benchmarking.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

HW/SW Acceleration of Multiple Workloads Within the SERRANO's Computing Continuum - Invited Paper.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

Application of Energy Efficient Filtering for UWB Indoor Positioning.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

An algorithm for node clustering targeting swarm of cyberphysical systems.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

Optimizing Savitzky-Golay Filter on GPU and FPGA Accelerators for Financial Applications.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

Approximate Decision Trees For Machine Learning Classification on Tiny Printed Circuits.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Design of A 10-Bit, 2GS/s Current-Steering Digital-to-Analog Converter with OnLine Current Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Dynamic Heap Management in High-Level Synthesis for Many-Accelerator Architectures.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021
Automated Design Approximation to Overcome Circuit Aging.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Leveraging HW Approximation for Exploiting Performance-Energy Trade-offs Within the Edge-Cloud Computing Continuum.
Proceedings of the High Performance Computing - ISC High Performance Digital 2021 International Workshops, Frankfurt am Main, Germany, June 24, 2021

Towards Efficient HW Acceleration in Edge-Cloud Infrastructures: The SERRANO Approach - Invited Paper.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Design considerations for a DC-DC Boost Converter in standard CMOS technology.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

Fatigue Detection Using Deep Long Short-Term Memory Autoencoders.
Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021


A Low-complexity, FPGA-based Maximum Power Point Tracking Circuit, for Wide Range Light-energy Harvesting.
Proceedings of the 2021 11th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS), 2021

Thermal Comfort Aware Online Energy Management Framework for a Smart Residential Building.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
Rapid Prototyping of Low-Complexity Orchestrator Targeting CyberPhysical Systems: The Smart-Thermostat Usecase.
IEEE Trans. Control. Syst. Technol., 2020

2019
VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019


Optimizing SVM Classifier Through Approximate and High Level Synthesis Techniques.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

ECG Analysis and Heartbeat Classification Based on Shallow Neural Networks.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

A Low-Complexity Framework for Distributed Energy Market Targeting Smart-Grid.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Design Flow Framework for Fully-Connected Neural Networks Rapid Prototyping.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

2018
OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures.
ACM Trans. Embed. Comput. Syst., 2018

Towards plug&play smart thermostats inspired by reinforcement learning.
Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

2017
On supporting rapid prototyping of embedded systems with reconfigurable architectures.
Integr., 2017

A Flexible Decision-Making Mechanism Targeting Smart Thermostats.
IEEE Embed. Syst. Lett., 2017

Algorithmic and memory optimizations on multiple application mapping onto FPGAs.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructure.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

FabSpace 2.0: A platform for application and service development based on Earth Observation data.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

An approach for estimating adulteration of virgin olive oil with soybean oil using image analysis.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Application performance improvement by exploiting process variability on FPGA devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Parameter Sensitivity in Virtual FPGA Architectures.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis.
ACM Trans. Embed. Comput. Syst., 2016

An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems.
ACM Trans. Embed. Comput. Syst., 2016

A Customizable Framework for Application Implementation onto 3-D FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization.
IEEE Embed. Syst. Lett., 2016

An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

2015
GENESIS: Parallel Application Placement onto Reconfigurable Architectures (Invited for the Special Issue on Runtime Management).
ACM Trans. Embed. Comput. Syst., 2015

An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs.
IEEE Embed. Syst. Lett., 2015

Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures.
IEEE Comput. Archit. Lett., 2015

A framework for reducing the modeling and simulation complexity of Cyberphysical Systems.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

A virtual platform for exploring hierarchical interconnection for many-accelerator systems.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
A Framework for Supporting Adaptive Fault-Tolerant Solutions.
ACM Trans. Embed. Comput. Syst., 2014

Plug&Chip: A Framework for Supporting Rapid Prototyping of 3D Hybrid Virtual SoCs.
ACM Trans. Embed. Comput. Syst., 2014

A framework for rapid evaluation of heterogeneous 3-D NoC architectures.
Microprocess. Microsystems, 2014

A novel 3-D FPGA architecture targeting communication intensive applications.
J. Syst. Archit., 2014

SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots.
J. Field Robotics, 2014

Co-design of many-accelerator heterogeneous systems exploiting virtual platforms.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014

A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks.
Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014

2013
JITPR: A framework for supporting fast application's implementation onto FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2013

A low-cost fault tolerant solution targeting commercial FPGA devices.
J. Syst. Archit., 2013

On supporting rapid exploration of memory hierarchies onto FPGAs.
J. Syst. Archit., 2013

A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC.
Int. J. Adapt. Resilient Auton. Syst., 2013

A Process-based Reconfigurable SystemC Module for simulation speedup.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems.
VLSI Design, 2012

A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric.
ACM Trans. Reconfigurable Technol. Syst., 2012

On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

FPGA-based path-planning of high mobility rover for future planetary missions.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Hardware implementation of stereo correspondence algorithm for the ExoMars mission.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A low-cost fault tolerant solution targeting to commercial FPGA devices.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

SPARTAN project: On profiling computer vision algorithms for rover navigation.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
A Tabu-Based Partitioning and Layer Assignment Algorithm for 3-D FPGAs.
IEEE Embed. Syst. Lett., 2011

On Supporting Rapid Thermal Analysis.
IEEE Comput. Archit. Lett., 2011

Thermal optimization for micro-architectures through selective block replication.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

A Framework for Architecture-Level Exploration of 3-D FPGA Platforms.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

CAD tools for designing 3D integrated systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Trading Fault-Masking with Performance Overhead for FPGAs.
Proceedings of the ARCS 2011, 2011

Quick_Hotspot: A Software Supported Methodology for Supporting Run-Time Thermal Analysis at MPSoC Designs.
Proceedings of the ARCS 2011, 2011

2010
A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures.
J. Circuits Syst. Comput., 2010

A Methodology for Alleviating the Performance Degradation of TMR Solutions.
IEEE Embed. Syst. Lett., 2010

Towards Supporting Fault-Tolerance in FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Multiple Vdd on 3D NoC architectures.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's.
Proceedings of the ARCS '10, 2010

A Framework for Enabling Fault Tolerance in Reconfigurable Architectures.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2009
Designing a novel high-performance FPGA architecture for data intensive applications.
J. Real Time Image Process., 2009

Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations.
Proceedings of the 16th International Conference on Digital Signal Processing, 2009

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays.
J. Low Power Electron., 2008

A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs.
J. Low Power Electron., 2008

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology.
Int. J. Reconfigurable Comput., 2008

A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007
A software-supported methodology for designing high-performance 3D FPGA architectures.
Proceedings of the IFIP VLSI-SoC 2007, 2007

A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.
Proceedings of the FPL 2007, 2007

Designing Heterogeneous FPGAs with Multiple SBs.
Proceedings of the Reconfigurable Computing: Architectures, 2007

2006
Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A novel methodology for designing high-performance and low-energy FPGA routing architecture.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005
A complete platform and toolset for system implementation on fine-grain reconfigurable hardware.
Microprocess. Microsystems, 2005

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications.
IEICE Trans. Inf. Syst., 2005

DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development.
Proceedings of the Field Programmable Logic and Application, 2004

2003
FPGA Architecture Design and Toolset for Logic Implementation.
Proceedings of the Integrated Circuit and System Design, 2003

Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms.
Proceedings of the Integrated Circuit and System Design, 2003

Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003


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