Kostas Masselos

Orcid: 0000-0001-9311-4696

Affiliations:
  • Imperial College London, UK


According to our database1, Kostas Masselos authored at least 83 papers between 1996 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Simulating Software Evolution to Evaluate the Reliability of Early Decision-making among Design Alternatives toward Maintainability.
ACM Trans. Softw. Eng. Methodol., May, 2023

Editorial: Infrastructure sharing in broadband networks: impact on telecommunications operators and consumers.
Frontiers Comput. Sci., 2023

2020
Experimental (raw) Data of Statistical Comparison Between Formal and Simulated Models' Outcomes for CIBI vs. CVP General Problem.
Dataset, May, 2020

A Locality Optimizer for Loop-dominated Applications Based on Reuse Distance Analysis.
ACM Trans. Design Autom. Electr. Syst., 2020

A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism.
ACM Trans. Embed. Comput. Syst., 2020

2017
Early Evaluation of Implementation Alternatives of Composite Data Structures Toward Maintainability.
ACM Trans. Softw. Eng. Methodol., 2017

A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors.
ACM Trans. Design Autom. Electr. Syst., 2017

2016
Compiler-Directed Data Locality Optimization in MATLAB.
Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Matlab to C compilation targeting Application Specific Instruction Set Processors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Automatic Generation of Code Analysis Tools: The CastQL Approach.
Proceedings of the 1st International Workshop on Real World Domain Specific Languages, 2016

2015
Reuse distance analysis for locality optimization in loop-dominated applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
An early memory hierarchy evaluation simulator for multimedia applications.
Microprocess. Microsystems, 2014

Hardware architecture for Fast 2D distance transformations.
Proceedings of the Sixth International Conference on Digital Image Processing, 2014

2013
Compiling Scilab to high performance embedded multicore systems.
Microprocess. Microsystems, 2013

Hardware design space exploration using HercuLeS HLS.
Proceedings of the 17th Panhellenic Conference on Informatics, 2013

The HercuLeS high-level synthesis environment.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Dynamic source code analysis for memory hierarchy optimization in multimedia applications.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012

A flexible approach for compiling scilab to reconfigurable multi-core embedded systems.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

From Scilab to High Performance Embedded Multicore Systems: The ALMA Approach.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Design of fixed-point rounding operators for the VHDL-2008 standard.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

MEMSCOPT: A source-to-source compiler for dynamic code analysis and loop transformations.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

XMSIM: A tool for early memory hierarchy evaluation.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

Automated Synthesis of FSMD-Based Accelerators for Hardware Compilation.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization.
Comput. J., 2011

2010
XMSIM: Extensible Memory Simulator for Early Memory Hierarchy Evaluation.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Efficient Hardware Looping Units for FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

System Level Design of Complex Hardware Applications Using ImpulseC.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2009
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems.
IET Comput. Digit. Tech., 2009

2008
Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs.
J. Signal Process. Syst., 2008

Outer Loop Pipelining for Application Specific Datapaths in FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Co-optimisation of datapath and memory in outer loop pipelining.
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework.
Proceedings of the FPL 2008, 2008

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation.
Proceedings of the Visions of Computer Science, 2008

2007
Implementation of Wireless Communications Systems on FPGA-Based Platforms.
EURASIP J. Embed. Syst., 2007

Prototyping of a WLAN system using C++ based architecture exploration.
Proceedings of the 3rd International Conference on Mobile Multimedia Communications, 2007

Automatic On-chip Memory Minimization for Data Reuse.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A comparison of 2-D discrete wavelet transform computation schedules on FPGAs.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

System Level Architecture Exploration for Reconfigurable Systems On Chip.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2004
Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors.
J. VLSI Signal Process., 2004

Embedded System Design Using Formal Model Refinement: An Approach Based on the Combined Use of UML and the B Language.
Des. Autom. Embed. Syst., 2004

Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.
Proceedings of the Integrated Circuit and System Design, 2004

A reusable IP FFT core for DSP applications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

System-Level Modeling of Dynamically Reconfigurable Co-processors.
Proceedings of the Field Programmable Logic and Application, 2004

SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip.
Proceedings of the Forum on specification and Design Languages, 2004

2003
High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations.
J. VLSI Signal Process., 2003

Power efficient data path synthesis of sum-of-products computations.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Realization of wireless multimedia communication systems on reconfigurable platforms.
J. Syst. Archit., 2003

Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications.
Des. Autom. Embed. Syst., 2003

Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms.
Proceedings of the Integrated Circuit and System Design, 2003

System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Energy Minimization Under Area and Performance Constraints for Multimedia Applications Realized on Embedded Cores.
VLSI Design, 2002

Power Efficient Hierarchical Scheduling for DSP Transformations.
VLSI Design, 2002

A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Memory accesses reordering for interconnect power reduction in sum-of-products computations.
IEEE Trans. Signal Process., 2002

Power Efficient Vector Quantization Design Using Pixel Truncation.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Cache misses and energy-dissipation results for JPEG-2000 filtering.
Proceedings of the 14th International Conference on Digital Signal Processing, 2002

Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations.
Proceedings of the Field-Programmable Logic and Applications, 2002

A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip.
Proceedings of the Field-Programmable Logic and Applications, 2002

2001
Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
Υψηλού επιπέδου μέθοδοι μείωσης της κατανάλωσης ενέργειας σε εφαρμογές πολυμέσων
PhD thesis, 2000

A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints.
J. VLSI Signal Process., 2000

Low power architectures for digital signal processing.
J. Syst. Archit., 2000

Low power synthesis of sum-of-products computation (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Development of a power efficient image coding algorithm based on integer wavelet transform.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999
Computation Reordering: A Novel Transformation for Low Power DSP Synthesis.
VLSI Design, 1999

Novel techniques for bus power consumption reduction in realizations of sum-of-product computation.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Strategy for power-efficient design of parallel systems.
IEEE Trans. Very Large Scale Integr. Syst., 1999

Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec.
J. Syst. Archit., 1999

A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Power exploration of multimedia applications realized on embedded cores.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Low power synthesis of sum-of-product computation in DSP algorithms.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

System-level power optimizing data-flow transformations for multimedia applications realized on programmable multimedia processors.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998
Trade-Off Analysis of a Low-Power Image Coding Algorithm.
J. VLSI Signal Process., 1998

A novel algorithm for low-power image and video coding.
IEEE Trans. Circuits Syst. Video Technol., 1998

Novel codebook generation algorithms for vector quantization image compression.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998

Low-power implementation of discrete wavelet transform.
Proceedings of the 9th European Signal Processing Conference, 1998

1996
Low-power image decoding using fractals.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

A parallel image compression scheme based on fractal coding and vector quantization.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996


  Loading...