Kostas Doris
According to our database1,
Kostas Doris
authored at least 21 papers
between 2008 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
32.6 A 76-to-81GHz Direct-Digital 7b 14GS/s Double-Balanced I/Q Mixing-DAC Radar-Waveform Synthesizer.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Time Interleaved ADC Mismatch Error Correction Technique in I/Q Digital Beamforming Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A novel analysis of the beam squinting in wideband phased array digital I/Q transmitters.
Proceedings of the European Conference on Circuit Theory and Design, 2020
2018
EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!).
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS.
IEEE J. Solid State Circuits, 2015
15.7 14b 35MS/S SAR ADC achieving 75dB SNDR and 99dB SFDR with loop-embedded input buffer in 40nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
An 11b 1GS/s ADC with parallel sampling architecture to enhance SNDR for multi-carrier signals.
Proceedings of the ESSCIRC 2013, 2013
2012
An 11b Pipeline ADC With Parallel-Sampling Technique for Converting Multi-Carrier Signals.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A 14 bit 200 MS/s DAC With SFDR > 78 dBc, IM3 < - 83 dBc and NSD < - 163 dBm/Hz Across the Whole Nyquist Band Enabled by Dynamic-Mismatch Mapping.
IEEE J. Solid State Circuits, 2011
A 480 mW 2.6 GS/s 10b Time-Interleaved ADC With 48.5 dB SNDR up to Nyquist in 65 nm CMOS.
IEEE J. Solid State Circuits, 2011
An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2008